Controlling the energy scales of a quantum system is essential for defining robust qubits. In silicon spin qubits, the nearly degenerate conduction-band valleys create a leakage channel from the single-spin computational basis, posing a challenge to scaling and to shuttling-based architectures. Here, we measure the relevant energy scales of single-electron spin qubits in buried silicon quantum wells co-designed for low disorder and high valley splitting. Across a linear array of four quantum dots with an average orbital energy of 2.4(2) meV, we report an average single-electron valley splitting of 0.40(6) meV and an average two-electron singlet-triplet splitting of 0.24(7) meV. In three dots, we observe a strong correlation between valley splitting and orbital energy, with an average linear coefficient of $\approx 0.22$ (meV/meV), demonstrating that electrostatic confinement can increase the valley splitting by several hundred microelectronvolts. In contrast, the remaining dot exhibits the highest valley splitting of 0.76(2) meV and low correlation, suggesting excellent characteristics for spin-qubit operation. Our findings demonstrate that strong confinement can be exploited in buried quantum wells to effectively enhance the valley splitting, thereby establishing a viable path toward the realization of shuttling and sparse-occupation-based architectures in low-disorder heterostructures.
Controlling the energy scales of a quantum system is essential for defining robust qubits. In silicon spin qubits, the nearly degenerate conduction-band valleys create a leakage channel from the single-spin computational basis, posing a challenge to scaling and to shuttling-based architectures. Here, we measure the relevant energy scales of single-electron spin qubits in buried silicon quantum wells co-designed for low disorder and high valley splitting. Across a linear array of four quantum dots with an average orbital energy of 2.4(2) meV, we report an average single-electron valley splitting of 0.40(6) meV and an average two-electron singlet-triplet splitting of 0.24(7) meV. In three dots, we observe a strong correlation between valley splitting and orbital energy, with an average linear coefficient of ≈0.22 (meV/meV), demonstrating that electrostatic confinement can increase the valley splitting by several hundred microelectronvolts. In contrast, the remaining dot exhibits the highest valley splitting of 0.76(2) meV and low correlation, suggesting excellent characteristics for spin-qubit operation. Our findings demonstrate that strong confinement can be exploited in buried quantum wells to effectively enhance the valley splitting, thereby establishing a viable path toward the realization of shuttling and sparse-occupation-based architectures in low-disorder heterostructures.
Achieving valley splittings well in excess of the thermal energy of electrons and avoiding valley excitations is essential for the consistent initialization, operation and readout of gate-defined Si spin qubits. In this work, we present a device-level optimization strategy for pushing valley splittings to between 1 and 5 meV, well beyond values reported in nearly all previous theoretical studies. Using device-scale simulations that incorporate atomistic alloy disorder through a 1D tight-binding theory, we demonstrate that our proposed approach yields large valley splittings with a tight distribution across disorder realizations, a key requirement for reproducible qubit performance at scale. The approach rests on an unorthodox Si/SiGe heterostructure design combining a narrow quantum well, a small Ge spike, and a pure-Ge cap. We corroborate these predictions with targeted atomistic density functional theory calculations. These results offer a clear path forward for scalable Si/SiGe spin qubit devices and, if realized experimentally, effectively eliminate valley splitting as an existential problem for large scale SiGe-based quantum processors.
While bulk silicon has long been understood to exhibit relatively weak spin-orbit coupling (SOC), confinement of electrons to quantum dots (QDs) at a silicon heterointerface results in significantly larger SOC. This is a concern for electron spin qubit performance, as intravalley and intervalley SOC can significantly perturb the operation of electron spin qubits. While these interactions can be harnessed to drive coherent rotations in a singlet-triplet qubit, coupling to low-lying excited valley states can lead to undesirable spin relaxation when valley splitting is on resonance with the Zeeman energy. In this work, we measure the angular dependence of the interfacial spin-orbit interaction as a function of the direction and magnitude of an applied external magnetic field in SiMOS and Si/SiGe heterostructures, two common material platforms for silicon spin qubits. We construct a physical model that accurately infers intra- and inter-valley SOC physics from fits to the data, allowing for a direct comparison between these two material systems. For the devices measured we find that, while the g-factor differences are comparable, the SiMOS QDs exhibit an order of magnitude larger spin-valley coupling than for Si/SiGe. Moreover, we find that the angular dependence of the spin-valley coupling is similar for both devices, with similar magnetic field orientations minimizing the spin-valley coupling. Our work points towards operational schemes for optimizing spin-valley coupling to avoid or exploit this mechanism for qubit operation.
Single spin quantum dot qubits in silicon are a promising candidate for a scalable quantum processor due to their long coherence times, compact size, and ease of integration into existing fabrication technologies. Realizing a large quantum processor composed of thousands or more logical qubits requires the integration of conventional transistor circuitry \nand wiring interconnects to control each individual dot in the processor. The high density of control wiring required for these processors presents many engineering challenges. In this thesis, we propose a surface code quantum processor for silicon quantum dot qubits based on a node/network architecture. Local nodes consisting of just seven quantum dots are \nspatially separated on the order of microns to facilitate space for the necessary high density wiring. Entanglement is distributed between individual nodes via shuttling of entangled electron pairs throughout the network. X or Z stabilizer operations, necessary for operating the surface code, are realized by distributing three electron spin singlet pairs across four local nodes followed by local gate operations and ancilla measurements. Simulations of electron shuttling indicate that adiabatic transport is possible on timescales that do not bottleneck the processor speed. Phase rotation of the shuttled spin, induced by the Stark shift, can lower the overall shuttling fi delity; however, the error can be mitigated by proper electrostatic tuning of the stationary electron's g-factor. Using realistic noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as \nsinglet dephasing errors during shuttling. Electron shuttling is a key resource of the proposed network architecture. We continue the shuttling simulations by presenting an algorithm for finding constant-adiabatic shuttling control pulses, which enables a more rigorous study of how different conditions impact the shuttling speed and fidelity. These constant adiabatic pulses are used to optimize the physical device geometry to maximize charge shuttling speeds up to 300 nm/ns in the single-valley case. We then switch to an effective Hamiltonian representation where spin and valley degrees of freedom are accounted for during shuttling. Using realistic device and material parameters, shuttle speeds in the range 10-100 nm/ns with high spin entanglement \n fidelities are obtained when the tunneling energy exceeds the Zeeman energy. High fidelity shuttling also requires the inter-dot valley phase difference to be below a threshold determined by the ratio of tunneling and Zeeman energies, so that spin-valley-orbit mixing is weak. In this regime, we find that the primary source of infi delity is a coherent spin rotation that is correctable, in principle, using single spin rotations. Two-qubit gates in the network architecture are mediated by the exchange interaction, \nan interaction that stems from the Coulomb interaction but manifests as a rotation between the |0,1> and |1,0> two qubit states. Realizing fault tolerant two-qubit gates has proven difficult in silicon quantum dots due to charge noise which perturbs the electron orbitals states, causing decoherence. Quantitatively accurate modelling of exchange in general quantum dot networks is important towards realizing fault tolerant gates. Traditional modelling methods, such as a full con figuration interaction approach, are cumbersome due to significant computational overhead required when accounting for the electron-electron interactions in the calculation. We present a modi ed linear combination of harmonic orbitals con figuration interaction (LCHO-CI) approach which signifi cantly reduces the computational time for obtaining quantitatively accurate estimations of exchange. The method works by approximating the single electron orbitals of the quantum dot network using an orthogonal basis of harmonic orbitals. This choice of orthogonal basis allows a precalculated library of matrix elements to be used in evaluating the Coulomb interactions, which speeds up the LCHO-CI calculation. The modi ed LCHO-CI approach is then used to study how the physical device geometry impacts the charge noise sensitivity of a double quantum dot system. We fi nd that, in general, geometries which increase the dot charging energy and decrease the gate lever arms improve the system's sensitivity to charge noise. We conclude this thesis by pivoting away from theoretical studies of silicon quantum dots and towards experimental studies of electron transport in dopant-free GaAs heterostructures. In modulation doped GaAs heterostructures, a doping layer is used to induce a two-dimensional electron gas (2DEG) at the heterojunction. Dopant-free GaAs lack the doping layer which makes fabrication more difficult as local electron reservoirs must be used to bring carriers and induce a 2DEG. The lack of the doping layer offers several advantages over modulation doped heterostructures, such as gate-ability of the 2DEG and ability to make ambipolar devices (both n- and p-type ohmic contacts). Realizing n- and p-type ohmic contacts requires etching a recess pit and depositing the ohmic material at an angle in order to preventing screening of the top gate when inducing a 2DEG or two-dimensional hole gas (2DHG). Magnetotransport experiments are used to characterize an induced 2DEG and 2DHG in a Hall bar fabricated on a 310 nm deep single heterojunction. The carrier mobility and density can be tuned using the top gate, and we achieve peak mobility values of 4.5E6 cm2/Vs and 0.65E6 cm2/Vs for the 2DEG and 2DHG respectively. We then move to a one-dimensional system and study electron transport through a quantum point contact. Conductance quantization is observed, and subband spectroscopy \nmeasurements indicate a 1D subband spacing of 4.5 meV. Finally, we study dynamically driven electron transport in a zero-dimensional system using a tunable-barrier quantum dot acting as a single electron pump. Single electron pumping is observed up to T = 5 K, and fi ts to the electron cascade model suggests pumping errors of 1.87 ppm when operated at a driving frequency of f = 500 MHz.
In Si(111) crystals, a strong biaxial tensile strain applied within the (111) plane is considered to shift the lowest energy point of the conduction band from the Δ valley to the L valley. Electrons confined in this L valley experience a splitting of their quadruply degenerate energy levels into an undegenerate single-level ground state (L1) and a triply degenerate excited state (L3). The energy of the single-level ground state is sufficiently low relative to the energies of the L3 valley and the Δ valley, making it optimal as a two-level system for a qubit. Using deformation potential theory and incorporating quantum effects from electron confinement in the SiGe/Si(111)/SiGe structure, we determine the value of the biaxial tensile strain causing the shift of the conduction band energy minimum from the Δ valley to the L valley, along with the corresponding Ge concentration. We also calculate the critical thickness for the plastic relaxation of the Si quantum well under this large biaxial tensile strain and examine the feasibility of realizing it as a SiGe/Si(111)/SiGe heterostructure.
Spatial variations of the valley splitting in a quantum well present a key challenge for conveyor-mode shuttling of electron spins in Si/SiGe, giving rise to Landau-Zener-like excitations that cause leakage outside the qubit subspace. Here, we propose an unconventional two-electron qubit encoding, based on valley-singlet states, that is largely immune to Landau-Zener leakage processes. In contrast to single-electron spins, the shuttling fidelity actually improves for small valley splittings, in this case. We show that high fidelities can be achieved without applying any special procedures, such as fine-tuning of the shuttling path.
Single electron spins can be used to encode and process information in semiconductor quantum devices. Progress has been hindered by materials challenges, such as the small energy splitting between low-lying valley states and hyperfine coupling to nuclear spins. Here we use density functional theory to optimize the valley splitting and spin dephasing time in realistic Si/SiGe heterostructures. Reductions in the Si quantum well width generally increase the valley splitting. However, in narrow quantum wells, a larger fraction of the electronic wavefunction resides in the SiGe buffer layers, which increases the hyperfine coupling with spinful 73Ge. Our work shows that Si/SiGe heterostructures with 3~--~4~nm wide quantum wells and 73Ge and 29Si concentrations of 50 ppm should support average valley splittings Ev~>~500~μeV and spin dephasing times T2∗ exceeding 15~μs assuming an effective quantum dot area of 700 nm2. In addition, sharper Si/SiGe interfaces in general result in larger valley splittings and longer spin dephasing times.