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arXiv:2606.30327

Phase-Altered Interleaved Randomized Benchmarking for Compiled Non-Clifford Gates

Simona K. Grigorova, Nikolay V. Vitanov, Boyan T. Torosov

quant-phSubmitted Jun 29, 2026• Announced Jun 30, 2026• 0 citations• Revised Oct 1, 2026 (v2)
v1 · Jun 29, 2026v2 · Oct 1, 2026
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Abstract

Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates. We introduce \emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports $Δr=r_d-r_s$ with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error. As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent $T/T^\dagger$ gates are implemented as virtual $Z$ rotations. Across tested calibration runs, $Δr$ is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.

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Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates.
We introduce \emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports Δr=rd−rsΔr=r_d-r_sΔr=rd​−rs​ with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error.
As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent T/T†T/T^\daggerT/T† gates are implemented as virtual ZZZ rotations. Across tested calibration runs, ΔrΔrΔr is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.
Accurate benchmarking of quantum gates is crucial for understanding and enhancing the performance of quantum hardware. A standard method for this is interleaved benchmarking, a technique which estimates the error on an interleaved target gate by comparing cumulative error rates of randomized sequences implemented with the interleaved gate and without it. In this work, we show both numerically and experimentally that the standard approach of interleaved randomized benchmarking (IRB), which uses the multi-qubit Clifford group for randomization, can produce highly inaccurate and even physically impossible estimates for the error on the interleaved gate in the presence of coherent errors. Fortunately we also show that interleaved benchmarking performed with cycle benchmarking, which randomizes with single qubit Pauli gates, provides dramatically reduced systematic uncertainty relative to standard IRB, and further provides as host of additional benefits including data reusability. We support our conclusions with a theoretical framework for bounding systematic errors, extensive numerical results comparing a range of interleaved protocols under fixed resource costs, and experimental demonstrations on three quantum computing platforms.
Cross-entropy benchmarking (XEB) with single-qubit reference sequences is widely used to characterize multi-qubit gates in large-scale quantum processors, despite the lack of a rigorous theoretical justification. Here we show that the commonly employed additive single-qubit errors approximation underlying this approach breaks down and leads to a systematic overestimation of gate fidelities. We derive an analytical expression for the joint decay of simultaneous single-qubit reference sequences, identify when interleaved circuits generate sufficient randomization for the standard depolarizing approximation, and obtain a refined expression for the interleaved gate fidelity estimation. Experiments on a superconducting quantum processor validate the theory and demonstrate that fidelities obtained using XEB with single-qubit references agree with those extracted from standard interleaved randomized benchmarking (IRB), while achieving higher precision due to reduced reference-sequence errors. Our results establish theoretical foundation for interleaved benchmarking protocols employing single-qubit reference sequences and show that, with appropriate post-processing, they provide a simple and accurate alternative to multi-qubit Clifford reference circuits.
Recently, there has been an emergence of useful applications for noisy intermediate-scale quantum (NISQ) devices notably, though not exclusively, in the fields of quantum machine learning and variational quantum algorithms. In such applications, circuits of various depths and composed of different sets of gates are run on NISQ devices. Therefore, it is crucial to find practical ways to capture the general performance of circuits on these devices. Motivated by this pressing need, we modified the standard Clifford randomized benchmarking (RB) and interleaved RB schemes targeting them to hardware limitations. Firstly we remove the requirement for, and assumptions on, the inverse operator, in Clifford RB by incorporating a tehchnique from quantum verification. This introduces another figure of merit by which to assess the quality of the NISQ hardware, namely the acceptance probability of quantum verification. Many quantum algorithms, that provide an advantage over classical algorithms, demand the use of Clifford as well as non-Clifford gates. Therefore, as our second contribution we develop a technique for characterising a variety of non-Clifford gates, by combining tools from gate synthesis with interleaved RB. Both of our techniques are most relevant when used in conjunction with RB schemes that benchmark generators (or native gates) of the Clifford group, and in low error regimes.
Abstract Randomized benchmarking is an important protocol for robustly characterizing the error rates of quantum gates. The technique is typically applied to the Clifford gates since they form a group that satisfies a convenient technical condition of forming a unitary 2-design, in addition to having a tight connection to fault-tolerant quantum computing and an efficient classical simulation. In order to achieve universal quantum computing one must add at least one additional gate such as the T gate (also known as the π /8 gate). Here we propose and analyze a simple variation of the standard interleaved RB protocol that can accurately estimate the average fidelity of the T gate while retaining the many advantages of a unitary 2-design and the fidelity guarantees that such a design delivers, as well as the efficient classical simulation property of the Clifford group. Our work complements prior methods that have succeeded in estimating T gate fidelities, but only by relaxing the 2-design constraint and using a more complicated data analysis.
Randomized benchmarking allows one to efficiently and scalably characterize the average error of a unitary 2-design such as the Clifford group C\mathcal{C}C on a physical candidate for quantum computation, as long as there are no noncomputational leakage levels in the system. We investigate the effect of leakage errors on randomized benchmarking induced from an additional level per physical qubit and provide a modified protocol that allows us to derive reliable estimates for the error per gate in their presence. We assess the variance of the sequence fidelity corresponding to the number of random sequences needed for valid fidelity estimation. Our protocol allows for gate-dependent error channels without being restricted to perturbations. We show that our protocol is compatible with interleaved randomized benchmarking and expand to benchmarking of arbitrary gates. This setting is relevant for superconducting transmon qubits, among other systems.