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arXiv:2606.21899

Shuttling in Bidimensional Segmented Ion-Trap Quantum Processors with T-Junctions

J. Durandau, C. A. Brunet, F. Schmidt-Kaler, U. Poschinger, F. Mailhot, Y. Bérubé-Lauzière

quant-phcs.ARSubmitted Jun 20, 2026• Announced Jun 23, 2026• 0 citations
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Abstract

Shuttle-based trapped ion quantum processors typically employ a one-dimensional (1D) linear architecture to transport ion-qubits between one ore more laser interaction zones where the quantum gates are implemented, along with several qubit register storage segments. The two-dimensional (2D) quantum CCD architecture employs also T- or X-junctions for an improved scaling and efficiency. Here, we explore the shuttling layer in the compilation of quantum algorithm typical building blocks in such architecture. To weight the effort of linear shuttle and junction shuttle, we introduce individual cost functions for each operation. This allows comparing the total cost for quantum circuit building blocks such as the QFT, Carry, Adder, Shift, and Comparator circuits. We study their scaling properties with increased qubit numbers. At equivalent transport cost for junction and linear shuttling, we show that 2D architectures outperform the 1D linear trap with the ratio improving as the number of ions increases. Finally, we discuss the use of cells, such that the entire processor is constructed from a 2D array of such interconnected cells. The work aims to optimize quantum processor architectures, implementing a co-design that fits to the specific task and scaling up in a shuttle-efficient way.

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Shuttle-based trapped ion quantum processors typically employ a one-dimensional (1D) linear architecture to transport ion-qubits between one ore more laser interaction zones where the quantum gates are implemented, along with several qubit register storage segments. The two-dimensional (2D) quantum CCD architecture employs also T- or X-junctions for an improved scaling and efficiency. Here, we explore the shuttling layer in the compilation of quantum algorithm typical building blocks in such architecture. To weight the effort of linear shuttle and junction shuttle, we introduce individual cost functions for each operation. This allows comparing the total cost for quantum circuit building blocks such as the QFT, Carry, Adder, Shift, and Comparator circuits. We study their scaling properties with increased qubit numbers. At equivalent transport cost for junction and linear shuttling, we show that 2D architectures outperform the 1D linear trap with the ratio improving as the number of ions increases. Finally, we discuss the use of cells, such that the entire processor is constructed from a 2D array of such interconnected cells. The work aims to optimize quantum processor architectures, implementing a co-design that fits to the specific task and scaling up in a shuttle-efficient way.
Current trapped-ion quantum computer architectures based on segmented traps utilize shuttling operations to establish connectivity between multiple sub-registers within one quantum processing unit. Complex trap architectures, including racetrack loops and junctions, offer prospects for increased scalability and have been successfully built and demonstrated. As hardware capabilities evolve, the need arises for additional automated software layers within the control stack for managing qubit routing. We present the automated generation of shuttling schedules for a branched ID architecture within a shuttling compiler that requires the integration of junctions. This not only provides the means for leveraging future new hardware advances, but also allows guiding the development of future architecture via resource estimation. Testing a wide range of quantum circuits, the junction-enabled shuttling compiler is able to reduce the necessary operations by a factor > 50 for translations and > 20 for separation/merge as compared to a linear architecture.
An algorithm for the generation of shuttling sequences is necessary for the operation of a linear segmented ion-trap quantum computer. The present work provides an implementation of an algorithm that produces sequences proved to be optimal for circuits with a quantum Fourier transform-like structure. Such optimality was proved in previous work of our group. We first present an approach for qubit mapping, i.e. determining the initial ordering of the ions, termed the common ion order, and develop a heuristic algorithm for its implementation. We explain how this heuristic is integrated in the shuttling sequence generation algorithm described in the previous work. The results show the increased performance of the heuristic in terms of reducing the number of required shuttling operations. The number of ion displacements required exhibits a polynomial increase in terms of the number of qubits, such that these operations become the main contribution to the overall resource cost. Furthermore, we show that multiple zones for gate interactions can reduce the amount of qubit register reordering.
Ion trap technologies have earned significant attention as potential candidates for quantum information processing due to their long decoherence times and precise manipulation of individual qubits, distinguishing them from other candidates in the field of quantum technologies. However, scalability remains a challenge, as introducing additional qubits into a trap increases noise and heating effects, consequently decreasing operational fidelity. Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures have addressed this limitation by interconnecting multiple traps and employing ion shuttling mechanisms to transfer ions among traps. This new architectural design requires the development of novel compilation techniques for quantum algorithms, which efficiently allocate and route qubits, and schedule operations. The aim of a compiler is to minimize ion movements and, therefore, reduce the execution time of the circuit to achieve a higher fidelity. In this paper, we propose a novel approach for initial qubit placement, demonstrating enhancements of up to 50% compared to prior methods. Furthermore, we conduct a scalability analysis on two distinct QCCD topologies: a 1D-linear array and a ring structure. Additionally, we evaluate the impact of the excess capacity - i.e. the number of free spaces within a trap - on the algorithm performance.
Trapped-ion quantum computer hardware is scaling to larger qubit numbers, but the computational capabilities of these devices remain largely unknown. From an abstract computer-science perspective, we address this problem in a two-step approach: First, we categorize levels of qubit connectivity for a processor based on ion-shuttling and individual ion addressing. Second, we apply computer-science techniques to develop optimized compilers that map arbitrary algorithms to sequences of ion-register reconfiguration and gate operations. We present compilers for 1D and 2D architectures, optimizing cost functions such as the qubit reconfiguration effort.
Scalable trapped-ion quantum computing is commonly realized with modular chips that feature distinct zones with specific functionalities, such as storage, state preparation, and gate execution. To execute a quantum circuit, the ions must be transported between these zones. This process is called ion shuttling. To achieve reliable computation results, the shuttling process must be optimized. However, as the number of ions increases, this becomes a high-dimensional optimization problem where optimal solutions cannot be computed efficiently. We demonstrate, to the best of our knowledge, the first use of reinforcement learning (RL) for the optimization of ion shuttling. RL is well-suited for such scenarios, as it enables learning a strategy through direct interaction with the problem. We show that our RL approach outperforms current state-of-the-art heuristic techniques, yielding a reduction in shuttling operations of up to 36.3 %. Furthermore, we show that our method is easily applicable to various chip architectures. Our approach offers a versatile method to study shuttling efficiency during chip design and, therefore, a highly relevant tool for future, more complex architectures.
Scaling quantum information processors is a challenging task, requiring manipulation of a large number of qubits with high fidelity and a high degree of connectivity. For trapped ions, this can be realized in a 2D array of interconnected traps in which ions are separated, transported, and recombined to carry out quantum operations on small subsets of ions. Here, functionality of a junction connecting orthogonal linear segments in a 2D trap array to reorder a two-ion crystal is demonstrated. The secular motion of the ions experiences low energy gain and the internal qubit levels maintain coherence during the reordering process, therefore demonstrating a promising method for providing all-to-all connectivity in a large-scale, 2D or 3D trapped-ion quantum information processor.