Current trapped-ion quantum computer architectures based on segmented traps utilize shuttling operations to establish connectivity between multiple sub-registers within one quantum processing unit. Complex trap architectures, including racetrack loops and junctions, offer prospects for increased scalability and have been successfully built and demonstrated. As hardware capabilities evolve, the need arises for additional automated software layers within the control stack for managing qubit routing. We present the automated generation of shuttling schedules for a branched ID architecture within a shuttling compiler that requires the integration of junctions. This not only provides the means for leveraging future new hardware advances, but also allows guiding the development of future architecture via resource estimation. Testing a wide range of quantum circuits, the junction-enabled shuttling compiler is able to reduce the necessary operations by a factor > 50 for translations and > 20 for separation/merge as compared to a linear architecture.
Current trapped-ion quantum computer architectures based on segmented traps utilize shuttling operations to establish connectivity between multiple sub-registers within one quantum processing unit. Complex trap architectures, including racetrack loops and junctions, offer prospects for increased scalability and have been successfully built and demonstrated. As hardware capabilities evolve, the need arises for additional automated software layers within the control stack for managing qubit routing. We present the automated generation of shuttling schedules for a branched ID architecture within a shuttling compiler that requires the integration of junctions. This not only provides the means for leveraging future new hardware advances, but also allows guiding the development of future architecture via resource estimation. Testing a wide range of quantum circuits, the junction-enabled shuttling compiler is able to reduce the necessary operations by a factor > 50 for translations and > 20 for separation/merge as compared to a linear architecture.
In trapped-ion quantum computers, qubits must be shuttled between segments to interact. The routing logic that schedules these movements is written by hand for every new trap architecture. We present shuttling compilers based on five large language models (LLMs). Each LLM is fine-tuned on shuttling schedules produced by hand-coded heuristics for linear and branched one-dimensional trap architectures. We investigate how the shuttling operation counts of their schedules compare with those of the heuristics and how far they generalize to unseen architectures. For circuits of up to 16 qubits, the fine-tuned LLMs generate valid schedules on both training architectures, more often the fewer qubits a circuit has. In 12% of the compilations yielding a schedule, the best of ten runs needs up to 21% fewer operations than the heuristic baselines, after a rule-based post-processing step. A single run of one fine-tuned LLM produces a valid shuttling schedule for a previously unseen four-way branched architecture. This is preliminary evidence of cross-architecture generalization. On two other unseen architectures no LLM produces a valid schedule. Thus, LLM-learned shuttling compilation is feasible, and we show how far it currently reaches.
Trapped-ion quantum computers rely on shuttling compilers, which cast an input algorithm into a sequence of ion-qubit movements within a given architecture. We present the first study in which a single frontier large language model (LLM), Claude Opus 4.7, generates and iteratively refines the Python code of shuttling compilers from written specifications. Starting with a compiler for (i) a linear segmented trap, we extend it to (ii) a trap with junctions, and finally achieve efficient compilation for (iii) a broad class of connected trap graphs. The compilers for the more general cases are seeded with code from the previous ones. We benchmark the LLM-generated compilers against state-of-the-art hand-crafted ones using a common suite of quantum circuits. The number of shuttling timesteps is reduced by up to 72% for (i) and up to 43% for (ii). For the broad case (iii) of freely connected architectures, we find large variations in the required number of shuttling timesteps, depending on the connectivity. A densely connected, junction-rich architecture yields up to an order-of-magnitude reduction in shuttling timesteps compared to a corridor-like one. Repeating the complete generation and evaluation with a second frontier LLM, Claude Fable 5, reproduces these findings, with the Fable 5 compilers surpassing the hand-crafted ones more often on the largest circuits. Our results show that an unmodified frontier LLM can produce working, correct, and competitive shuttling compilers without additional manual algorithmic engineering. Generating compilers this way reduces the development time for new architectures from several months to a few days.
A promising approach for scaling-up trapped-ion quantum computer platforms is by storing multiple trapped-ion qubit sets ('ion crystals') in segmented microchip traps and to interconnect these via physical movement of the ions ('shuttling'). Already for realizing quantum circuits with moderate complexity, the design of suitable qubit assignments and shuttling schedules require automation. Here, we describe and test algorithms which address exactly these tasks. We describe an algorithm for fully automated generation of shuttling schedules, complying to constraints imposed by a given trap structure. Furthermore, we introduce different methods for initial qubit assignment and compare these for random circuit (of up to 20 qubits) and quantum Fourier transform-like circuits, and generalized Toffoli gates of up to 40 qubits each. We find that for quantum circuits which contain a fixed structure, advanced assignment algorithms can serve to reduce the shuttling overhead.
Shuttle-based trapped ion quantum processors typically employ a one-dimensional (1D) linear architecture to transport ion-qubits between one ore more laser interaction zones where the quantum gates are implemented, along with several qubit register storage segments. The two-dimensional (2D) quantum CCD architecture employs also T- or X-junctions for an improved scaling and efficiency. Here, we explore the shuttling layer in the compilation of quantum algorithm typical building blocks in such architecture. To weight the effort of linear shuttle and junction shuttle, we introduce individual cost functions for each operation. This allows comparing the total cost for quantum circuit building blocks such as the QFT, Carry, Adder, Shift, and Comparator circuits. We study their scaling properties with increased qubit numbers. At equivalent transport cost for junction and linear shuttling, we show that 2D architectures outperform the 1D linear trap with the ratio improving as the number of ions increases. Finally, we discuss the use of cells, such that the entire processor is constructed from a 2D array of such interconnected cells. The work aims to optimize quantum processor architectures, implementing a co-design that fits to the specific task and scaling up in a shuttle-efficient way.
An algorithm for the generation of shuttling sequences is necessary for the operation of a linear segmented ion-trap quantum computer. The present work provides an implementation of an algorithm that produces sequences proved to be optimal for circuits with a quantum Fourier transform-like structure. Such optimality was proved in previous work of our group. We first present an approach for qubit mapping, i.e. determining the initial ordering of the ions, termed the common ion order, and develop a heuristic algorithm for its implementation. We explain how this heuristic is integrated in the shuttling sequence generation algorithm described in the previous work. The results show the increased performance of the heuristic in terms of reducing the number of required shuttling operations. The number of ion displacements required exhibits a polynomial increase in terms of the number of qubits, such that these operations become the main contribution to the overall resource cost. Furthermore, we show that multiple zones for gate interactions can reduce the amount of qubit register reordering.
Shuttling-based trapped-ion quantum computers (QCCD) rank among the most mature hardware platforms. Existing and envisaged devices exhibit architectural differences in terms of register layout and connectivity. Platform-specific compilers are required to translate quantum circuits into resource-optimized hardware-level command chains. Hardware platforms and compiler software stacks are mostly developed independently of one another by different research communities. This work aims to bridge these communities by abstracting QCCD architectures and native operations, enabling computer scientists to address compilation problems using generic methods without requiring a deep background in the physical operating principles of the platform. The resulting design space is organized into a small set of architectural archetypes, each posing its own compilation problem. We then select and apply compilation methods to one- and two-dimensional QCCD architectures, finding that the routing overhead scales approximately cubically with the number of qubits for the one-dimensional architecture and approximately quadratically for the two-dimensional one. Extending this to compilation with a quantum error-correction layer reveals additional differences and similarities between the physical and logical levels. We conclude that co-design is a requirement rather than an option, and this work provides the vocabulary, archetypes, and compilation abstraction it needs.