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arXiv:2605.08792

A Controlled Study of Memory Hierarchy Transitions in Quantum Circuit Simulation on Apple M4 Pro Unified Memory Architecture

Gyan Pratipat

cs.PFquant-phSubmitted May 9, 2026• Announced May 12, 2026• 0 citations• Revised Oct 1, 2026 (v3)
v1 · May 9, 2026v2 · May 12, 2026v3 · Oct 1, 2026
arXivHTMLPDF

Abstract

State-vector quantum circuit simulation is memory-bandwidth bound, yet the interaction between memory hierarchy, access pattern, and hardware parallelism remains incompletely characterized. We address this using the Apple M4 Pro Unified Memory Architecture (UMA), where CPU and GPU share identical physical LPDDR5X DRAM ($\sim$224 GB/s STREAM bandwidth for both), eliminating memory-technology and interconnect confounds. Using a thermally isolated, multi-trial methodology across 11 simulation backends on GHZ and QFT circuits from 3 to 30 qubits, we make three central contributions. First, a Roofline analysis confirms all gate implementations have arithmetic intensity $\leq$0.38 FLOP/byte, well below the ridge point for any plausible peak compute on modern hardware, establishing structural memory-boundedness. Second, we identify a reproducible 4.46$\times$ timing discontinuity at the 28$\rightarrow$29 qubit transition, confirmed under thermally isolated conditions and cross-validated across GHZ and QFT circuits; tensordot backends exhibit the full discontinuity while direct-index backends maintain $\sim$2$\times$ per-qubit scaling throughout. Third, despite STREAM predicting only 1.85$\times$ GPU speedup (MLX CPU 119.9 GB/s vs. MLX GPU 221.9 GB/s), all three algorithm classes exceed this prediction: tensordot 3.1--4.1$\times$, flat-index 3.5--5.9$\times$, and direct-index 6--10$\times$, demonstrating that peak streaming bandwidth does not predict simulation speedup for non-contiguous memory access patterns, with the gap widening as access irregularity increases. These findings provide a hardware-characterization framework for quantum simulation workloads on UMA.

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9 Pages, 5 Figures, 7 Tables

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physics.geo-phCross-listedarXiv:2611.01176•Nov 3, 2026
State-vector quantum circuit simulation is memory-bandwidth bound, yet the interaction between memory hierarchy, access pattern, and hardware parallelism remains incompletely characterized. We address this using the Apple M4 Pro Unified Memory Architecture (UMA), where CPU and GPU share identical physical LPDDR5X DRAM (∼\sim∼224 GB/s STREAM bandwidth for both), eliminating memory-technology and interconnect confounds. Using a thermally isolated, multi-trial methodology across 11 simulation backends on GHZ and QFT circuits from 3 to 30 qubits, we make three central contributions. First, a Roofline analysis confirms all gate implementations have arithmetic intensity ≤\leq≤0.38 FLOP/byte, well below the ridge point for any plausible peak compute on modern hardware, establishing structural memory-boundedness. Second, we identify a reproducible 4.46×\times× timing discontinuity at the 28→\rightarrow→29 qubit transition, confirmed under thermally isolated conditions and cross-validated across GHZ and QFT circuits; tensordot backends exhibit the full discontinuity while direct-index backends maintain ∼\sim∼2×\times× per-qubit scaling throughout. Third, despite STREAM predicting only 1.85×\times× GPU speedup (MLX CPU 119.9 GB/s vs. MLX GPU 221.9 GB/s), all three algorithm classes exceed this prediction: tensordot 3.1--4.1×\times×, flat-index 3.5--5.9×\times×, and direct-index 6--10×\times×, demonstrating that peak streaming bandwidth does not predict simulation speedup for non-contiguous memory access patterns, with the gap widening as access irregularity increases. These findings provide a hardware-characterization framework for quantum simulation workloads on UMA.
Classical simulation of quantum circuits remains indispensable for algorithm development, hardware validation, and error analysis in the noisy intermediate-scale quantum (NISQ) era. However, state-vector simulation faces exponential memory scaling, with an n-qubit system requiring O(2^n) complex amplitudes, and existing simulators often lack the flexibility to exploit heterogeneous computing resources at runtime. This paper presents a GPU-accelerated quantum circuit simulation framework that introduces three contributions: (1) an empirical backend selection algorithm that benchmarks CuPy, PyTorch-CUDA, and NumPy-CPU backends at runtime and selects the optimal execution path based on measured throughput; (2) a directed acyclic graph (DAG) based gate fusion engine that reduces circuit depth through automated identification of fusible gate sequences, coupled with adaptive precision switching between complex64 and complex128 representations; and (3) a memory-aware fallback mechanism that monitors GPU memory consumption and gracefully degrades to CPU execution when resources are exhausted. The framework integrates with Qiskit, Cirq, PennyLane, and Amazon Braket through a unified adapter layer. Benchmarks on an NVIDIA A100-SXM4 (40 GiB) GPU demonstrate speedups of 64x to 146x over NumPy CPU execution for state-vector simulation of circuits with 20 to 28 qubits, with speedups exceeding 5x from 16 qubits onward. Hardware validation on an IBM quantum processing unit (QPU) confirms Bell state fidelity of 0.939, a five-qubit Greenberger-Horne-Zeilinger (GHZ) state fidelity of 0.853, and circuit depth reduction from 42 to 14 gates through the fusion pipeline. The system is designed for portability across NVIDIA consumer and data-center GPUs, requiring no vendor-specific compilation steps.
The classical simulation of quantum algorithms is a crucial tool for circuit development, testing, and validation. Although acceleration using GPUs significantly reduces simulation time, most high-performance simulators rely on vendor-specific frameworks that target data-center hardware. To broaden access to quantum simulation, this work proposes a vendor-agnostic approach targeting the integrated GPUs commonly found in consumer-grade laptops. A primary challenge in state-vector simulation is its inherently poor spatial locality, which creates a memory bandwidth bottleneck. Consequently, baseline implementations experience a severe degradation in relative GPU speedup as the number of simulated qubits increases. To address this limitation, we introduce a state partitioning optimization that reorganizes the quantum state vector to maximize the last-level cache locality and minimize costly main memory fetches. We evaluate this strategy using a Quantum Phase Estimation algorithm across diverse architectures from Intel, AMD, and Apple. The experimental results demonstrate that the proposed optimization successfully mitigates performance degradation at larger qubit scales. In particular, for a 28-qubit simulation, the optimization reversed a performance deficit on an Intel Core i5, improving the GPU speedup over the CPU from 0.95x to 1.89x, and increased the Apple M1 Pro speedup from 3.71x to 5.88x. Overall, this approach yields consistent execution time improvements, demonstrating the viability of integrated GPUs for efficient quantum circuit simulation.
We present Qupertino, an open-source quantum circuit simulator for Apple Silicon, and use it to ask how far a simulator written purely in MLX array operations can go and what remains for hand-tuned Metal shaders. The framework ships two measured tiers. The pure tier dispatches structured gates to specialized MLX kernels: diagonal gates run as broadcast phase multiplies, controlled gates as masked half-state updates, and SWAP as an axis permutation; a paired dense-path ablation attributes a 25-33x speedup to this dispatch alone. The opt-in shader tier adds hand-written Metal kernels for every structured layer family in our benchmarks, including phase-LUT diagonals, GF(2) affine permutation gathers, fused tensor-product single-qubit layers, radix-4 QFT and Walsh-Hadamard butterflies, and basis-conjugated XX/YY Trotter layers; runtime fusion detectors route work to them while preserving circuit semantics exactly, confirmed by parity tests. In a four-way interleaved campaign on M1 Max (two warmups, ten measured repeats per cell), the shader tier is fastest by mean runtime in all 18 comparison cells against same-machine Qiskit Aer CPU and PennyLane lightning.qubit. At 25 qubits, gate-stream QFT runs in 0.0591 +/- 0.0029 s (paired 47.2x over Aer, 95.3x over PennyLane) and TFIM Trotter evolution in 0.495 +/- 0.035 s (36.2x and 67.2x). Across a 29-workload suite, the shader tier's paired speedup over pure MLX reaches 25x, with 25 of 29 workloads accelerating above parity. The framework also supports variational ansatz workloads, QAOA, QCBM, Trotter-Suzuki Hamiltonian simulation, and OpenQASM 2.0 import (unitary subset); a preliminary MPS backend reaches 150 qubits on limited-entanglement workloads. Correctness rests on 253 Python tests, independent complex128 checks, and a Trotter-error curve against exact diagonalization. State-vector memory remains exponential in qubit count.
Abstract This paper presents a distributed quantum circuit statevector simulator thatpartitions the full 2n-amplitude state vector across four Xilinx Alveo U55C field-programmable gate arrays, each equipped with eight gigabytes of HBM2. Thearchitecture assigns two top-index qubits as partition bits so that card j ownsall amplitudes whose binary index has bits [n − 2, n − 1] equal to j, givingeach card a local statevector of 2n−2 complex double-precision amplitudes inter-leaved across eight HBM banks under a modulo-eight scheme. Gate executionis divided into three paths: local gates (acting on qubit indices below n − 2)are dispatched directly to the on-card HLS kernel; diagonal gates acting on par-tition qubits (controlled-phase, RZ , phase, CZ) are applied as a scalar phasemultiply without any cross-card data movement; and non-diagonal partition-qubit gates (Hadamard, CNOT) are handled by a three-barrier, double-bufferedshared-memory exchange followed by vectorised host arithmetic. This diagonal-gate local path eliminates cross-card traffic for every controlled-phase gate ina Quantum Fourier Transform, which would otherwise constitute the dominantcommunication bottleneck in a distributed QFT implementation.We validate the system across five quantum algorithm families on real hardware.The Quantum Fourier Transform achieves state fidelity F = 1.000000000000against an independent Qiskit statevector reference for all circuit widths fromn = 4 to n = 18 qubits, with wall-clock times ranging from 0.96 s at fourqubits to 19.1 s at eighteen qubits. Grover search circuits on up to ten qubitsachieve target-state probability exceeding 99.9% in all cases, with measuredfidelity F = 1.0 confirming exact computation on the FPGA hardware. GHZstate preparation, Bell pair generation, QFT–IQFT round-trips, and a nine-qubitShor algorithm component all pass at F = 1.000000000000. At twenty qubits, where each card holds 218 = 262,144 amplitudes consuming four megabytes ofHBM per card, the simulation completes correctly in under two minutes.Compared with the prior single-FPGA 30-qubit statevector engine, the distributed architecture extends the qubit ceiling to 28 qubits (4 GB total HBM)with exact complex128 precision, and removes the routing failure that prevented a sixteen-bank single-kernel design from placing on the XCVU55C. Comparedwith the Matrix Product State engine at 500 qubits, the statevector approachremains exact for arbitrary entanglement, at the cost of exponential memoryscaling rather than polynomial. The companion real-time quantum error correc-tion kernels and the native RTL statevector design together constitutea complete FPGA quantum computing stack, and the multi-FPGA distributedarchitecture presented here occupies the high-fidelity large-scale simulation tierof that stack.
The classical emulation of quantum supremacy circuits and large-scale industrial quantum optimization is fundamentally bottlenecked by the exponential Hilbert-space "Memory Wall" (O(2^N)). Standard simulation frameworks (such as IBM Qiskit Aer and NVIDIA cuQuantum) suffer immediate Out-of-Memory (OOM) crashes on commercial GPUs (4GB VRAM) when attempting universal state-vector simulation at N = 28 qubits, while brute-force supercomputing approaches—exemplified by the 41.9-million-core New Sunway system—require 1.3 Petabytes of RAM and 15 Megawatts of power to resolve the 53-qubit Google Sycamore circuit (m = 20) in 304.4 seconds. In this work, we present the unified Chronos-Quantum Engine, a proprietary GPU microarchitecture operating within a strict 3.58 GB VRAM ceiling on a single 60W laptop GPU (NVIDIA RTX 3050 Ti). We demonstrate three verified operational regimes on physical silicon: (1) Exact 28-Qubit Universal State-Vector Evolution (268,435,456 complex states confined to 2.147 GB VRAM) achieving IEEE-754 exactness (L2 error = 8.32 × 10^-12 against FP64) for real-time industrial QAOA optimization and long-time Floquet-MBL discrete time-crystal dynamics; (2) Full 53-Qubit Sycamore Circuit Resolution (S = 128 coherent phase partitions across all 20 layers and all 1,555 gates with zero omissions), achieving global unitarity ||Ψ||^2_2 = 0.99998384, unbiased Porter-Thomas second moment ⟨u2⟩/⟨u⟩2 = 2.014852 (0.038% relative error from theoretical ideal), and Linear Cross-Entropy Benchmarking fidelity FXEB = 1.014852 (1.039321 under Born quantile sampling) in 372.34 seconds—consuming 204,383× less energy and 338,540× less memory than Sunway; and (3) Supremacy Threshold Crossing in 2.96 seconds (Slice 1, FXEB = 0.0235 > 0.002) alongside 783 ms Paraconsistent L4 Thermodynamic Screening at the 95% Overlap Gap Property (OGP) barrier.
Quantum circuit simulators are essential for quantum algorithm development, yet systematic runtime benchmarks comparing major frameworks across CPU and GPU backends are limited. We benchmark three open-source frameworks - Cirq (qsim), CUDA-Q, and Qiskit (Aer) - on statevector simulation of the 2D quantum acoustic wave equation, evolved via Trotterized Hamiltonian dynamics, for problem sizes from 7 to 29 qubits on a single Azure virtual machine. The evaluation spans four categories: CPU runtime versus qubit count, strong scalability on multi-core CPUs at 27 qubits, GPU runtime versus qubit count, and GPU-over-CPU speedup. Relative rankings shift from one category to the next. On CPU, Cirq is fastest up to 23 qubits (2.4x faster than Qiskit at 21 qubits), but Qiskit overtakes it at larger sizes and higher thread counts, sustaining 80% parallel efficiency at 16 threads. On GPU, CUDA-Q leads between 13 and 21 qubits, while Cirq becomes the fastest GPU backend at large problem sizes, achieving 1.5x and 2.3x speedups over CUDA-Q and Qiskit at 29 qubits. GPU-over-CPU speedup ratios should be interpreted alongside absolute GPU runtimes; CUDA-Q's 1500x at 21 qubits is largely driven by the limited scaling of its CPU backend (qpp), and the absolute GPU runtimes show that the three frameworks' GPU backends differ by less than these ratios alone suggest. These results indicate that no single framework dominates across configurations, and that backend selection for statevector simulation should be guided by both target hardware and problem size.