We present Qupertino, an open-source quantum circuit simulator for Apple Silicon, and use it to ask how far a simulator written purely in MLX array operations can go and what remains for hand-tuned Metal shaders. The framework ships two measured tiers. The pure tier dispatches structured gates to specialized MLX kernels: diagonal gates run as broadcast phase multiplies, controlled gates as masked half-state updates, and SWAP as an axis permutation; a paired dense-path ablation attributes a 25-33x speedup to this dispatch alone. The opt-in shader tier adds hand-written Metal kernels for every structured layer family in our benchmarks, including phase-LUT diagonals, GF(2) affine permutation gathers, fused tensor-product single-qubit layers, radix-4 QFT and Walsh-Hadamard butterflies, and basis-conjugated XX/YY Trotter layers; runtime fusion detectors route work to them while preserving circuit semantics exactly, confirmed by parity tests. In a four-way interleaved campaign on M1 Max (two warmups, ten measured repeats per cell), the shader tier is fastest by mean runtime in all 18 comparison cells against same-machine Qiskit Aer CPU and PennyLane lightning.qubit. At 25 qubits, gate-stream QFT runs in 0.0591 +/- 0.0029 s (paired 47.2x over Aer, 95.3x over PennyLane) and TFIM Trotter evolution in 0.495 +/- 0.035 s (36.2x and 67.2x). Across a 29-workload suite, the shader tier's paired speedup over pure MLX reaches 25x, with 25 of 29 workloads accelerating above parity. The framework also supports variational ansatz workloads, QAOA, QCBM, Trotter-Suzuki Hamiltonian simulation, and OpenQASM 2.0 import (unitary subset); a preliminary MPS backend reaches 150 qubits on limited-entanglement workloads. Correctness rests on 253 Python tests, independent complex128 checks, and a Trotter-error curve against exact diagonalization. State-vector memory remains exponential in qubit count.
We present Qupertino, an open-source quantum circuit simulator for Apple Silicon, and use it to ask how far a simulator written purely in MLX array operations can go and what remains for hand-tuned Metal shaders. The framework ships two measured tiers. The pure tier dispatches structured gates to specialized MLX kernels: diagonal gates run as broadcast phase multiplies, controlled gates as masked half-state updates, and SWAP as an axis permutation; a paired dense-path ablation attributes a 25-33x speedup to this dispatch alone. The opt-in shader tier adds hand-written Metal kernels for every structured layer family in our benchmarks, including phase-LUT diagonals, GF(2) affine permutation gathers, fused tensor-product single-qubit layers, radix-4 QFT and Walsh-Hadamard butterflies, and basis-conjugated XX/YY Trotter layers; runtime fusion detectors route work to them while preserving circuit semantics exactly, confirmed by parity tests. In a four-way interleaved campaign on M1 Max (two warmups, ten measured repeats per cell), the shader tier is fastest by mean runtime in all 18 comparison cells against same-machine Qiskit Aer CPU and PennyLane lightning.qubit. At 25 qubits, gate-stream QFT runs in 0.0591 +/- 0.0029 s (paired 47.2x over Aer, 95.3x over PennyLane) and TFIM Trotter evolution in 0.495 +/- 0.035 s (36.2x and 67.2x). Across a 29-workload suite, the shader tier's paired speedup over pure MLX reaches 25x, with 25 of 29 workloads accelerating above parity. The framework also supports variational ansatz workloads, QAOA, QCBM, Trotter-Suzuki Hamiltonian simulation, and OpenQASM 2.0 import (unitary subset); a preliminary MPS backend reaches 150 qubits on limited-entanglement workloads. Correctness rests on 253 Python tests, independent complex128 checks, and a Trotter-error curve against exact diagonalization. State-vector memory remains exponential in qubit count.
State-vector quantum circuit simulation is memory-bandwidth bound, yet the interaction between memory hierarchy, access pattern, and hardware parallelism remains incompletely characterized. We address this using the Apple M4 Pro Unified Memory Architecture (UMA), where CPU and GPU share identical physical LPDDR5X DRAM ($\sim$224 GB/s STREAM bandwidth for both), eliminating memory-technology and interconnect confounds. Using a thermally isolated, multi-trial methodology across 11 simulation backends on GHZ and QFT circuits from 3 to 30 qubits, we make three central contributions. First, a Roofline analysis confirms all gate implementations have arithmetic intensity $\leq0.38FLOP/byte,wellbelowtheridgepointforanyplausiblepeakcomputeonmodernhardware,establishingstructuralmemory−boundedness.Second,weidentifyareproducible4.46\times$ timing discontinuity at the 28$\rightarrow$29 qubit transition, confirmed under thermally isolated conditions and cross-validated across GHZ and QFT circuits; tensordot backends exhibit the full discontinuity while direct-index backends maintain $\sim2\times$ per-qubit scaling throughout. Third, despite STREAM predicting only 1.85× GPU speedup (MLX CPU 119.9 GB/s vs. MLX GPU 221.9 GB/s), all three algorithm classes exceed this prediction: tensordot 3.1--4.1×, flat-index 3.5--5.9×, and direct-index 6--10×, demonstrating that peak streaming bandwidth does not predict simulation speedup for non-contiguous memory access patterns, with the gap widening as access irregularity increases. These findings provide a hardware-characterization framework for quantum simulation workloads on UMA.
Classical simulation of quantum circuits remains indispensable for algorithm development, hardware validation, and error analysis in the noisy intermediate-scale quantum (NISQ) era. However, state-vector simulation faces exponential memory scaling, with an n-qubit system requiring O(2^n) complex amplitudes, and existing simulators often lack the flexibility to exploit heterogeneous computing resources at runtime. This paper presents a GPU-accelerated quantum circuit simulation framework that introduces three contributions: (1) an empirical backend selection algorithm that benchmarks CuPy, PyTorch-CUDA, and NumPy-CPU backends at runtime and selects the optimal execution path based on measured throughput; (2) a directed acyclic graph (DAG) based gate fusion engine that reduces circuit depth through automated identification of fusible gate sequences, coupled with adaptive precision switching between complex64 and complex128 representations; and (3) a memory-aware fallback mechanism that monitors GPU memory consumption and gracefully degrades to CPU execution when resources are exhausted. The framework integrates with Qiskit, Cirq, PennyLane, and Amazon Braket through a unified adapter layer. Benchmarks on an NVIDIA A100-SXM4 (40 GiB) GPU demonstrate speedups of 64x to 146x over NumPy CPU execution for state-vector simulation of circuits with 20 to 28 qubits, with speedups exceeding 5x from 16 qubits onward. Hardware validation on an IBM quantum processing unit (QPU) confirms Bell state fidelity of 0.939, a five-qubit Greenberger-Horne-Zeilinger (GHZ) state fidelity of 0.853, and circuit depth reduction from 42 to 14 gates through the fusion pipeline. The system is designed for portability across NVIDIA consumer and data-center GPUs, requiring no vendor-specific compilation steps.
Quantum circuit simulators are essential for quantum algorithm development, yet systematic runtime benchmarks comparing major frameworks across CPU and GPU backends are limited. We benchmark three open-source frameworks - Cirq (qsim), CUDA-Q, and Qiskit (Aer) - on statevector simulation of the 2D quantum acoustic wave equation, evolved via Trotterized Hamiltonian dynamics, for problem sizes from 7 to 29 qubits on a single Azure virtual machine. The evaluation spans four categories: CPU runtime versus qubit count, strong scalability on multi-core CPUs at 27 qubits, GPU runtime versus qubit count, and GPU-over-CPU speedup. Relative rankings shift from one category to the next. On CPU, Cirq is fastest up to 23 qubits (2.4x faster than Qiskit at 21 qubits), but Qiskit overtakes it at larger sizes and higher thread counts, sustaining 80% parallel efficiency at 16 threads. On GPU, CUDA-Q leads between 13 and 21 qubits, while Cirq becomes the fastest GPU backend at large problem sizes, achieving 1.5x and 2.3x speedups over CUDA-Q and Qiskit at 29 qubits. GPU-over-CPU speedup ratios should be interpreted alongside absolute GPU runtimes; CUDA-Q's 1500x at 21 qubits is largely driven by the limited scaling of its CPU backend (qpp), and the absolute GPU runtimes show that the three frameworks' GPU backends differ by less than these ratios alone suggest. These results indicate that no single framework dominates across configurations, and that backend selection for statevector simulation should be guided by both target hardware and problem size.
Hybrid quantum-classical machine learning workflows repeatedly evaluate many small parametrized circuits during training and model exploration. In this regime, framework dispatch and orchestration overhead often dominate runtime. Prior simulators accelerate execution but leave open the question of when compile-once specialization is the right choice for static variational circuits. We answer this question with VQCSim, a compile-once, PyTorch-native statevector execution path with native autograd. In a systematic MQT Bench study, VQCSim compiles all tested static circuits and provides 87.7% end-to-end semantic validation. Across a five-GPU evaluation set, VQCSim delivers pooled median speedups of 4.49x for native inference and 26.78x for native training, while retaining a 3.31x advantage under matched finite-difference training. Ablation identifies native autograd as the dominant source of acceleration (27.6x), with compile-once caching and batch vectorization contributing additional gains. The speedup trades higher GPU memory (VQCSim is memory-limited at the high end) for lower runtime. We derive a hardware-aware regime map and release vqcsim-oracle, an open-source backend selector with 91.1%-97.7% top-1 agreement (including cross-GPU transfers), enabling automatic simulator selection in QML design loops.
This Zenodo upload contains the complete evaluation data, benchmark suites, and preprint manuscript for SuperFermion: A Leap Forward in Quantum Circuit Simulation Efficiency. The study evaluates SuperFermion against prominent open-source quantum simulation frameworks—including Qiskit Aer, PennyLane, Cirq, Qulacs, and Stim—across multiple execution paradigms: Statevector Learning: Assesses 252 identical conditions (4 to 20 qubits) across quantum kernel estimation (QSVM, QKRR, QKPCA), variational learning (VQC, VQR), combinatorial optimization (QAOA, VQE), and circuit sweeps, totaling 1,512 simulator jobs. Matrix Product States (MPS) & Dynamic Circuits: Explores bounded entanglement, canonical tensor structures, and mid-circuit measurements/feed-forward operations, scaling structured circuits up to 1,000 qubits and native MPS teleportation to 120 qubits. Specialized Execution Modes: Examines compiled adjoint gradients, dense-core density matrices, and a unified binary stabilizer/Clifford tableau sampling engine across up to 4,096 qubits. The repository provides source-traceable verification logs, JSONL/CSV records, capability probes, analysis scripts, and an integrated manuscript comprising comprehensive performance tables and scaling figures.
Abstract This paper presents a distributed quantum circuit statevector simulator thatpartitions the full 2n-amplitude state vector across four Xilinx Alveo U55C field-programmable gate arrays, each equipped with eight gigabytes of HBM2. Thearchitecture assigns two top-index qubits as partition bits so that card j ownsall amplitudes whose binary index has bits [n − 2, n − 1] equal to j, givingeach card a local statevector of 2n−2 complex double-precision amplitudes inter-leaved across eight HBM banks under a modulo-eight scheme. Gate executionis divided into three paths: local gates (acting on qubit indices below n − 2)are dispatched directly to the on-card HLS kernel; diagonal gates acting on par-tition qubits (controlled-phase, RZ , phase, CZ) are applied as a scalar phasemultiply without any cross-card data movement; and non-diagonal partition-qubit gates (Hadamard, CNOT) are handled by a three-barrier, double-bufferedshared-memory exchange followed by vectorised host arithmetic. This diagonal-gate local path eliminates cross-card traffic for every controlled-phase gate ina Quantum Fourier Transform, which would otherwise constitute the dominantcommunication bottleneck in a distributed QFT implementation.We validate the system across five quantum algorithm families on real hardware.The Quantum Fourier Transform achieves state fidelity F = 1.000000000000against an independent Qiskit statevector reference for all circuit widths fromn = 4 to n = 18 qubits, with wall-clock times ranging from 0.96 s at fourqubits to 19.1 s at eighteen qubits. Grover search circuits on up to ten qubitsachieve target-state probability exceeding 99.9% in all cases, with measuredfidelity F = 1.0 confirming exact computation on the FPGA hardware. GHZstate preparation, Bell pair generation, QFT–IQFT round-trips, and a nine-qubitShor algorithm component all pass at F = 1.000000000000. At twenty qubits, where each card holds 218 = 262,144 amplitudes consuming four megabytes ofHBM per card, the simulation completes correctly in under two minutes.Compared with the prior single-FPGA 30-qubit statevector engine, the distributed architecture extends the qubit ceiling to 28 qubits (4 GB total HBM)with exact complex128 precision, and removes the routing failure that prevented a sixteen-bank single-kernel design from placing on the XCVU55C. Comparedwith the Matrix Product State engine at 500 qubits, the statevector approachremains exact for arbitrary entanglement, at the cost of exponential memoryscaling rather than polynomial. The companion real-time quantum error correc-tion kernels and the native RTL statevector design together constitutea complete FPGA quantum computing stack, and the multi-FPGA distributedarchitecture presented here occupies the high-fidelity large-scale simulation tierof that stack.