Quantum simulation of fermionic Hamiltonians is a leading application of quantum computing, but accurate execution on present-day hardware is limited by error accumulation in deep Trotter circuits. We present a device-matched noise-reduction framework for encoded Hamiltonian simulation that combines symplectic-transvection-based Trotter synthesis in the Generalized Superfast Encoding (GSE) with Clifford Noise Reduction (CliNR) and Shor-style stabilizer verification enabled by mid-circuit measurement. We implement this approach for a six-qubit encoded Clifford Trotter step on a Barium development system similar to the forthcoming IonQ Tempo line and benchmark it against direct execution using both hardware experiments and a calibrated device-level noise model. The encoded CliNR execution achieves up to 54% lower logical error rate. Crucially, this advantage disappears when stabilizer readout is deferred to the end of the circuit, showing that timely mid-circuit fault detection, rather than verification overhead alone, drives the improvement. As a proof of concept, we further show that machine-learning-guided stabilizer selection can identify verification operators that outperform random choices. These results demonstrate that encoding-native verification combined with dynamic-circuit primitives can materially improve application-motivated quantum simulation without the full overhead of quantum error correction.
Quantum simulation of fermionic Hamiltonians is a leading application of quantum computing, but accurate execution on present-day hardware is limited by error accumulation in deep Trotter circuits. We present a device-matched noise-reduction framework for encoded Hamiltonian simulation that combines symplectic-transvection-based Trotter synthesis in the Generalized Superfast Encoding (GSE) with Clifford Noise Reduction (CliNR) and Shor-style stabilizer verification enabled by mid-circuit measurement. We implement this approach for a six-qubit encoded Clifford Trotter step on a Barium development system similar to the forthcoming IonQ Tempo line and benchmark it against direct execution using both hardware experiments and a calibrated device-level noise model. The encoded CliNR execution achieves up to 54% lower logical error rate. Crucially, this advantage disappears when stabilizer readout is deferred to the end of the circuit, showing that timely mid-circuit fault detection, rather than verification overhead alone, drives the improvement. As a proof of concept, we further show that machine-learning-guided stabilizer selection can identify verification operators that outperform random choices. These results demonstrate that encoding-native verification combined with dynamic-circuit primitives can materially improve application-motivated quantum simulation without the full overhead of quantum error correction.
We propose several optimizations of the CliNR partial error correction scheme which implements Clifford circuits by consuming a resource state. Errors are corrected by measuring a sequence of Pauli operators that we refer to as the verification sequence. We first propose a global optimization algorithm searching for a verification sequence resulting in a low logical error rate using tabu search. Then, we introduce a proxy for the logical error rate which is easier to evaluate and we design a two-step optimization algorithm. First, a verification sequence minimizing the proxy is computed, then this sequence is refined by reintroducing the logical error rate. Finally, we identify a large group of automorphisms of the search space which preserve the proxy and we use this symmetry to reduce the size of the search space. This results in a 168 × (respectively 20,160 × ) reduction of the size of the search space for the optimization of verification sequences with three (respectively four) Pauli operators. Our numerical simulations for 20-qubit Clifford circuits with size 400 under the ion chain model show that our optimization algorithms improve the performance of CliNR by 25% and that the two-step optimization achieves the same results as the global optimization with 64% fewer evaluations of the logical error rate. Finally, we perform experiments on a 36-qubit trapped ion quantum computer, without mid-circuit measurements, showing that the CZNR variant of CliNR is at breakeven.
Simulating molecular systems on quantum computers requires efficient mappings from Fermionic operators to qubit operators. Traditional mappings such as Jordan-Wigner or Bravyi-Kitaev often produce high-weight Pauli terms, increasing circuit depth and measurement complexity. Although several local qubit mappings have been proposed to address this challenge, most are specialized for structured models like the Hubbard Hamiltonian and perform poorly for realistic chemical systems with dense two-body interactions. In this work, we utilize a suite of techniques to construct compact and noise-resilient Fermion-to-qubit mappings suitable for general molecular Hamiltonians. Building on the Generalized Superfast Encoding (GSE) and other similar works, we demonstrate that it outperforms prior encodings in both accuracy and hardware efficiency for molecular simulations. Our improvements include path optimization within the Hamiltonian's interaction graph to minimize operator weight, introduction of multi-edge graph structures for enhanced error detection without added circuit depth, and a stabilizer measurement framework that directly maps logical terms and stabilizers to the Z-basis using Clifford simulation. Applying these methods to simulations of (H2)2 and (H2)3 systems yields significantly improved absolute and correlation energy estimates under realistic hardware noise, with further accuracy gains achieved by increasing code distance. We also propose a [[2N, N, 2]] variant of GSE compatible with square-lattice and (quasi-)linear hardware topologies, demonstrating a twofold reduction in RMSE for orbital rotations on IBM Kingston hardware. These results establish GSE as a very attractive mapping for molecular quantum simulations.
Dynamic quantum circuits integrate mid-circuit measurements and feed-forward operations to enable real-time classical processing and conditional quantum logic. These capabilities are central to key quantum protocols such as quantum error correction, and have recently demonstrated significant potential for reducing quantum resources, including circuit depth and gate count, across a range of applications. However, executing dynamic circuits on real quantum hardware introduces a critical trade-off: while resource requirements decrease, circuit fidelity degrades due to high error rates of mid-circuit measurements, as well as the decoherence errors accumulated during the extended idle periods introduced by both mid-circuit measurements and feed-forward operations. In this paper, we systematically investigate the impact of standard error mitigation techniques on dynamic circuit applications pertaining to Hamiltonian simulation and ground state estimation of physically relevant systems like the Heisenberg model. We explore dynamical decoupling (DD) as a strategy to suppress decoherence and crosstalk errors during idle windows introduced by mid-circuit measurements and feed-forward delays, and also examine error mitigation via zero-noise extrapolation (ZNE). Through experiments conducted on IBM quantum hardware, we benchmark effective combinations of these strategies that maximize the practical benefits of dynamic quantum circuits in these applications. We demonstrate that a combination of DD and ZNE is effective in mitigating the errors introduced during mid-circuit measurements and feed-forward operations, as well as the errors arising from faulty measurements. This approach yields a energy gap improvement of at least 60% in ground state estimation and reduces observed error of time-evolved states by up to 99% for the Ising model and up to 20% for the Heisenberg model.
We propose a Clifford noise reduction (CliNR) scheme that provides a reduction of the logical error rate of Clifford circuit with lower overhead than error correction and without the exponential sampling overhead of error mitigation. CliNR implements Clifford circuits by splitting them into subcircuits that are performed using gate teleportation. A few random stabilizer measurements are used to detect errors in the resources states consumed by the gate teleportation. This can be seen as a teleported version of the coherent parity-check scheme [1-3], with offline fault-detection making it scalable. We prove that CliNR achieves a vanishing logical error rate for families of n-qubit Clifford circuits with size s such that nsp^{2} goes to 0, where p is the physical error rate, meaning that it reaches the regime ns=o(1/p^{2}), whereas the direct implementation is limited to s=o(1/p). Moreover, CliNR uses only 3n+1 qubits, 2s+o(s) gates and has zero rejection rate. This small overhead makes it more practical than quantum error correction in the near term and our numerical simulations show that CliNR provides a reduction of the logical error rate in relevant noise regimes.
Small high-rate non-CSS stabilizer codes provide compact platforms for encoded quantum computation, but mixed-Pauli checks and limited native transversal logical gates complicate fault-tolerant dynamics. Block-level constructions offer an alternative by mapping an entire logical block to a physical circuit rather than compiling separately protected logical gates. We investigate this approach using the high-rate [[8,3,3]] non-CSS code and logical Trotter circuits as a testbed. We construct flagged syndrome-extraction circuits and establish a circuit-level memory pseudo-threshold near 1.5×10−3. We then apply our symplectic-transvection construction, which maps a logical Trotter circuit to a physical circuit with the same block pattern for any stabilizer code. Although this mapping preserves the intended unitary algebraically, encoded Trotter circuits exhibit asymmetry between logical-X and logical-Z failure channels. Single-fault analysis identifies the mechanism: a fault on the shared parity ancilla can propagate through the uncomputation network into an undetectable logical operator, reducing the effective circuit distance in the affected sector. We evaluate flag-conditioned recovery, biased-noise decoding, CliNR resource verification, flag postselection, and asymmetric gate-noise models. These methods suppress propagated faults but do not simultaneously suppress both logical sectors in the realistic configurations studied. A diagnostic protected limit removing the identified malignant first-order locations restores pseudo-threshold behavior in both sectors, approaching memory performance. These results demonstrate the potential of block-level logical constructions for non-CSS codes without rich native transversal gate sets and the joint protection of the parity network, analog rotation, and recovery required to preserve fault-tolerant distance.
Clifford noise reduction (CliNR) is a partial error correction scheme that reduces the logical error rate of Clifford circuits at the cost of a modest qubit and gate overhead. The CliNR implementation of an n-qubit Clifford circuit of size s achieves a vanishing logical error rate if snp2→0 where p is the physical error rate. Here, we propose a recursive version of CliNR that can reduce errors on larger circuits with a relatively small gate overhead. When np→0, the logical error rate can be vanishingly small. This implementation requires (2⌈log(sp)⌉+3)n+1 qubits and at most $24 s \left\lceil(sp)^4\right\rceil $ gates. Using numerical simulations, we show that the recursive method can offer an advantage in a realistic near-term parameter regime. When circuit sizes are large enough, recursive CliNR can reach a lower logical error rate than the original CliNR with the same gate overhead. The results offer promise for reducing logical errors in large Clifford circuits with relatively small overheads.