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arXiv:2604.13632

A $\boldsymbol{2d \times d \times d}$ Spacetime Volume Implementation of a Logical S Gate in the Surface Code

Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki

quant-phSubmitted Apr 15, 2026• Announced Apr 16, 2026• 0 citations
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Abstract

The logical S gate implemented via twist defect braiding in the surface code is one of the major sources of overhead in fault-tolerant quantum computing, since an S-gate correction is required in every logical T-gate teleportation. Existing logical S-gate implementations require spacetime volumes of \(2d \times 2d \times d\) or \(2d \times 1.5d \times d\), where $d$ is the code distance of the surface code. To the best of our knowledge, their circuit-level implementations have not yet been shown, hindering quantitative comparisons of fault distances and logical error rates. In this work, we provide these missing circuit-level implementations. Additionally, we propose a novel twist defect braiding protocol that reduces the spacetime volume to \(2d \times d \times d\). First, we construct an implementation of the proposed method using constant-length non-local gates, and then refine it to utilize only nearest-neighbor two-qubit gates on a square grid, without requiring additional two-qubit gate depth beyond that of standard syndrome extraction circuits. Through numerical simulations, we evaluate the fault distances and logical error rates for both existing and proposed methods. Our results show that, although the proposed method reduces the fault distance by one or three, its logical error rates remain comparable to those of existing methods at large code distances (\(d \ge 5\)) and at physical error rates near \(p = 10^{-3}\). This demonstrates that the proposed method is promising for near-term fault-tolerant quantum computing.

Comments
16 pages, 22 figures

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A 2d×d×d\boldsymbol{2d \times d \times d}2d×d×d Spacetime Volume Implementation of a Logical S Gate in the Surface Code
The logical S gate implemented via twist defect braiding in the surface code is one of the major sources of overhead in fault-tolerant quantum computing, since an S-gate correction is required in every logical T-gate teleportation. Existing logical S-gate implementations require spacetime volumes of (2d \times 2d \times d) or (2d \times 1.5d \times d), where ddd is the code distance of the surface code. To the best of our knowledge, their circuit-level implementations have not yet been shown, hindering quantitative comparisons of fault distances and logical error rates. In this work, we provide these missing circuit-level implementations. Additionally, we propose a novel twist defect braiding protocol that reduces the spacetime volume to (2d \times d \times d). First, we construct an implementation of the proposed method using constant-length non-local gates, and then refine it to utilize only nearest-neighbor two-qubit gates on a square grid, without requiring additional two-qubit gate depth beyond that of standard syndrome extraction circuits. Through numerical simulations, we evaluate the fault distances and logical error rates for both existing and proposed methods. Our results show that, although the proposed method reduces the fault distance by one or three, its logical error rates remain comparable to those of existing methods at large code distances ((d \ge 5)) and at physical error rates near (p = 10^{-3}). This demonstrates that the proposed method is promising for near-term fault-tolerant quantum computing.
One of the most promising routes towards fault-tolerant quantum computation utilizes topological quantum error correcting codes, such as the Z2{\mathbb{Z}}_{2}Z2​ surface code. Logical qubits can be encoded in a variety of ways in the surface code, based on either boundary defects, holes, or bulk twist defects. However, proposed fault-tolerant implementations of the Clifford group in these schemes are limited and often require unnecessary overhead. For example, the Clifford phase gate in certain planar and hole encodings has been proposed to be implemented using costly state injection and distillation protocols. In this paper, we show that within any encoding scheme for the logical qubits, we can fault tolerantly implement the full Clifford group by using joint measurements involving a single appropriately encoded logical ancilla. This allows us to provide low overhead implementations of the full Clifford group in surface and color codes. It also provides the first proposed implementations of the full Clifford group in hyperbolic codes. We further use our methods to propose state-of-the art encoding schemes for small numbers of logical qubits; for example, for code distances d=3,5,7d=3,5,7d=3,5,7, we propose a scheme using 60,160,30860,160,30860,160,308 (respectively) physical data qubits, which allow for the full logical Clifford group to be implemented on two logical qubits. To our knowledge, this is the optimal proposal to date, and thus may be useful for demonstration of fault-tolerant logical gates in small near-term quantum computers.
The surface code is one of the leading quantum error correction codes for realizing large-scale fault-tolerant quantum computing (FTQC). One major challenge in realizing surface-code-based FTQC is the extremely large number of qubits required. To mitigate this problem, fusing multiple codewords of the surface code into a densely packed configuration has been proposed. It is known that by using dense packing, the number of physical qubits required per logical qubit can be reduced to approximately three-fourths compared to simply placing surface-code patches side by side. Despite its potential, concrete deformation procedures and quantitative error-rate analyses have remained largely unexplored. In this work, we present a detailed code-deformation procedure that transforms multiple standard surface code patches into a densely packed, connected configuration, along with a conceptual microarchitecture to utilize this dense packing. We also propose a CNOT gate-scheduling for stabilizer measurement circuits that suppresses hook errors in the densely packed surface code. We performed circuit-level Monte Carlo noise simulation of densely packed surface codes using this gate scheduling. The numerical results demonstrate that as the code distance of the densely packed surface code increases and the physical error rate decreases, the logical error rate of the densely packed surface code becomes lower than that of the standard surface code. Furthermore, we find that only when employing hook-error-avoiding syndrome extraction can the densely packed surface code achieve a lower logical error rate than the standard surface code, while simultaneously reducing the space overhead.
The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors---permanent faulty components such as missing physical qubits or failed entangling gates---introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive swap gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of swap gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of 88%8 qubit fabrication errors, the surface code can still tolerate a computational error rate of up to 0.10.1%0.1.
Hook errors are a major challenge in implementing logical operations with the surface code, because they can reduce the fault distance below the code distance. This motivates syndrome-extraction circuits that suppress hook-error effects for the stabilizer layouts that appear during logical operations. However, the existing methods either increase circuit depth or require simultaneous execution of measurements and CNOT gates, both of which introduce additional overheads and degrade the threshold. We propose the ZX interleaving syndrome extraction, which preserves the full fault distance ddd for any surface-code layout with regular stabilizer tiles at minimum depth, i.e., four layers of CNOT gates, without requiring additional circuit depth or simultaneous execution of measurements and CNOT gates. The key idea is to interleave the Z and X stabilizer tiles so that hook-error edges in the decoding graph are shortened and effectively eliminated. Numerical simulations under uniform depolarizing noise for memory and lattice-surgery experiments confirm that the proposed method achieves a full fault distance of ddd, whereas the best existing minimum-depth approach achieves d−1d-1d−1. Since the full fault distance is achievable for any regular tiling layout of the surface code, the proposed method may serve as an indispensable technique for practical fault-tolerant quantum computation.
Majorana zero modes (MZMs) are promising candidates for topologically-protected quantum computing hardware, however their large-scale use will likely require quantum error correction. Majorana surface codes (MSCs) have been proposed to achieve this. However, many MSC properties remain unexplored. We present a unified framework for MSC "twist defects" – anyon-like objects encoding quantum information. We show that twist defects in MSCs can encode twice the amount of topologically protected information as in qubit-based codes or other MSC encoding schemes. This is due to twists encoding both logical qubits and "logical MZMs," with the latter enhancing the protection microscopic MZMs can offer. We explain how to perform universal computation with logical qubits and logical MZMs while potentially using far fewer resources than in other MSC schemes. All Clifford gates can be implemented on logical qubits by braiding twist defects. We introduce lattice-surgery-based techniques for computing with logical MZMs and logical qubits, achieving the effect of Clifford gates with zero time overhead. We also show that logical MZMs may result in improved spatial overheads for sufficiently low rates of quasi-particle poisoning. Finally, we introduce a novel MSC analogue of transversal gates that achieves encoded Clifford gates in small codes by braiding microscopic MZMs. MSC twist defects thus open new paths towards fault-tolerant quantum computation.
High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.