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arXiv:2603.27231

Ultralow-power coherent qubit control using AQFP logic at millikelvin temperatures

Hiroto Mukai, Akiyoshi Tomonaga, Rui Wang, Yu Zhou, Taro Yamashita, Nobuyuki Yoshikawa, Jaw-Shen Tsai, Naoki Takeuchi

quant-phSubmitted Mar 28, 2026• Announced Mar 31, 2026• 0 citations
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Abstract

Qubit controllers are essential for scaling superconducting quantum processors, but implementing them at the 10 mK stage of a dilution refrigerator remains challenging due to stringent cooling constraints. Here we report an ultralow-power qubit controller using adiabatic quantum-flux-parametron (AQFP) logic, termed an AQFP-multiplexed qubit controller with virtual Z gates (AQFP QC-VZ). The AQFP QC-VZ generates multi-tone microwave pulses for qubit control with an ultralow power dissipation of 111 pW per qubit. By combining microwave and time-division multiplexing, the AQFP QC-VZ enables parallel application of X and virtual Z gates to multiple qubits using only a few control lines from room temperature. We demonstrate coherent single-qubit gates at the 10 mK stage using an AQFP mixer, a core component of the AQFP QC-VZ, without observable degradation in coherence.

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11 pages, 5 figures

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Qubit controllers are essential for scaling superconducting quantum processors, but implementing them at the 10 mK stage of a dilution refrigerator remains challenging due to stringent cooling constraints. Here we report an ultralow-power qubit controller using adiabatic quantum-flux-parametron (AQFP) logic, termed an AQFP-multiplexed qubit controller with virtual Z gates (AQFP QC-VZ). The AQFP QC-VZ generates multi-tone microwave pulses for qubit control with an ultralow power dissipation of 111 pW per qubit. By combining microwave and time-division multiplexing, the AQFP QC-VZ enables parallel application of X and virtual Z gates to multiple qubits using only a few control lines from room temperature. We demonstrate coherent single-qubit gates at the 10 mK stage using an AQFP mixer, a core component of the AQFP QC-VZ, without observable degradation in coherence.
Abstract Cryogenic qubit controllers (QCs) are the key to build large-scale superconducting quantum processors. However, developing scalable QCs is challenging because the cooling power of a dilution refrigerator is too small (~10 μW at ~10 mK) to operate conventional logic families, such as complementary metal-oxide-semiconductor logic and superconducting single-flux-quantum logic, near qubits. Here we report on a scalable QC using an ultra-low-power superconductor logic family, namely adiabatic quantum-flux-parametron (AQFP) logic. The AQFP-based QC, referred to as the AQFP-multiplexed QC (AQFP-mux QC), produces multi-tone microwave signals for qubit control with an extremely small power dissipation of 81.8 pW per qubit. Furthermore, the AQFP-mux QC adopts microwave multiplexing to reduce the number of coaxial cables for operating the entire system. As a proof of concept, we demonstrate an AQFP-mux QC chip that produces microwave signals at two output ports through microwave multiplexing and demultiplexing. Experimental results show an output power of approximately −80 dBm and on/off ratio of ~40 dB at each output port. Basic mixing operation is also demonstrated by observing sideband signals.
Quantum processors have the potential to accelerate specific computing tasks but are difficult to scale up due to engineering limitations, such as the number of available cables and cooling power for dilution refrigerators for quantum bits (qubits). Hence, it is very important to develop scalable, energy-efficient interface circuits that can control many qubits via a few control lines inside a dilution refrigerator. One of the most important interface circuits is the flux controller (FC), which generates arbitrary dc flux bias to adjust the characteristics of component devices such as qubits. In this paper, we propose and demonstrate FCs using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. We develop two types of FCs: the AQFP FC and the AQFP/single-flux-quantum (AQFP/SFQ) FC. Both FCs require only a few control lines and have extremely small power dissipation, thus exhibiting high scalability. Furthermore, the AQFP/SFQ FC can control flux bias using ballistic SFQ transmission, which is crucial for integration with qubits. As a proof of concept, we demonstrate AQFP and AQFP/SFQ FCs at 4.2 K, fabricated by the AIST high-speed standard process. Our results indicate that AQFP logic is highly suitable for use as qubit interface circuits for very large-scale quantum processors, especially from the viewpoint of the control line count, power dissipation, and amount of supply currents.
Quantum technologies are today regarded as one of the key technologies with huge implications to technological, economic and social developments in the next decades. Among the different platforms, superconducting implementations represent one of the most promising and are therefore pursued by several research institutions but also by numerous high-tech companies. Current research focusses e.g. on scaling towards a large number of qubits needed for practical implementations of this technology. Amongst the various realizations, adiabatic quantum flux parametron (AQFP) circuits have shown lowest power dissipation reaching Landauer limit. The operation of AQFP circuits down to mK temperature has been recently demonstrated. We will present a new concept for a digital control circuit based on the microwave pulse patters generated by single flux quantum circuits operating at mK temperatures. We discuss the circuit operation and the integration together with superconducting qubits to a compact and scalable approach for multi-Qubit control by digital pulse patterns.
Readout and control of qubits are limiting factors in scaling quantum computers. An ideal solution is to integrate energy-efficient cryogenic circuits close to the qubits to perform control and pre-processing tasks. With orders of magnitude lower power consumption and hence lower noise, Single Flux Quantum (SFQ) and Adiabatic Quantum Flux Parametron (AQFP) superconductor logic families can reach ultimate performance at cryogenic temperatures. We have created a superconductor-based on-chip function generator to control qubits. The generated signal is modulated up to tens of GHz based on the external input waveform applied to the superconductor mixer stage. This circuit works at 4.2K. A radiofrequency (RF) matching circuit transmits the signal to the ~mK stage after digital amplification and noise reduction.
Current superconducting quantum computers (QC) rely on a brute-force scaling approach where quantum chips operating at the millikelvin stage inside dilution refrigerators are connected to room-temperature electronics via an ever-increasing number of signal wires. In order to drastically scale up such systems without facing refrigeration challenges, these quantum interface electronics need to be integrated at cryogenic temperatures, ideally at the same stage as qubits. In this paper, we show that, by employing energy-efficient digital superconducting microchips based on single flux quantum (SFQ) technology, all essential functions to operate a full stack quantum computer can be integrated at 10 mK. They include digital qubit charge control and magnetic flux control for single- and two-qubit gates, as well as digital qubit readout.
Adiabatic quantum-flux-parametron (AQFP) logic is a highly energy-efficient superconductor logic family. Traditionally, AQFP circuits have relied on the four-phase clocking scheme, which uses a pair of ac current sources with a 90° phase difference. The operation of each logic gate thus takes a quarter clock cycle, leading to a relatively long latency for some applications. In this Letter, we propose a low-latency clocking scheme for AQFP logic based on microwave power dividers (PDs). The whole circuit is powered by a single excitation current, which is equally split for each logic stage by a serial-type PD. As a result, the latency between adjacent logic stages is determined by the transmission line length (propagation delay) inside the PD, which can be much shorter than a quarter clock cycle. Note that the low-latency performance is independent of the horizontal length of the AQFP circuit, and thus, the proposed clocking scheme is applicable to large-scale designs where a large number of gates are horizontally placed in a single stage. For validation, several numerical simulations are conducted and a six-stage AQFP test circuit is demonstrated using the proposed power-dividing clocking scheme (with a designed latency of 20 ps per gate) at a temperature of 4.2 K.