© 2026 Aqora Quantum S.A.S.

Terms Privacy Legal Notice

arXiv:2602.05900 · APS Open Science

Reducing the Computational Cost Scaling of Tensor Network Algorithms via Field-Programmable Gate Array Parallelism

Songtai Lv, Yang Liang, Rui Zhu, Qibin Zheng, Haiyuan Zou

cond-mat.str-elcond-mat.stat-mechhep-latquant-phSubmitted Feb 5, 2026• Announced Feb 6, 2026• 1 citation• Revised Oct 29, 2026 (v2)

v1 · Feb 5, 2026 v2 · Oct 29, 2026

Abstract

Improving the computational efficiency of quantum many-body calculations from a hardware perspective remains a critical challenge. Although field-programmable gate arrays (FPGAs) have recently been exploited to improve the computational scaling of algorithms such as Monte Carlo methods, their application to tensor network algorithms is still at an early stage. In this work, we propose a fine-grained parallel tensor network design based on FPGAs to substantially enhance the computational efficiency of two representative tensor network algorithms: the infinite time-evolving block decimation (iTEBD) and the higher-order tensor renormalization group (HOTRG). By employing a quad-tile partitioning strategy to decompose tensor elements and map them onto hardware circuits, our approach effectively translates algorithmic computational complexity into scalable hardware resource utilization, enabling an extremely high degree of parallelism on FPGAs. Compared with conventional CPU-based implementations, our scheme exhibits superior scalability in computation time, reducing the bond-dimension scaling of the computational cost from $O(D_b^3)$ to $O(D_b)$ for iTEBD and from $O(D_b^6)$ to $O(D_b^2)$ for HOTRG. This work provides a theoretical foundation for future hardware implementations of large-scale tensor network computations.

Journal reference: APS Open Sci. 1, 000064 (2026)
DOI: 10.1103/ktzw-t6fx
Comments: 9 pages, 5 figures

Related papers

Many-body computing on Field Programmable Gate Arrays

Songtai Lv, Yang Liang, Yuchen Meng +5 more

Abstract A new implementation of many-body calculations is of paramount importance in the field of computational physics. In this study, we leverage the capabilities of Field Programmable Gate Arrays (FPGAs) for conducting quantum many-body calculations. Through the design of appropriate schemes for Monte Carlo and tensor network methods, we effectively utilize the parallel processing capabilities provided by FPGAs. This has resulted in a remarkable tenfold speedup compared to CPU-based computation for a Monte Carlo algorithm. We also demonstrate, for the first time, the utilization of FPGA to accelerate a typical tensor network algorithm. Our findings unambiguously highlight the significant advantages of hardware implementation and pave the way for novel approaches to many-body calculations.

arXiv:2402.06415•Communications Physics•Mar 25, 2025•4 citations

FPGA acceleration of tensor network computing for quantum spin models

Yang Liang, Songtai Lv, Zhiping Tang +3 more

Increasing the degree of freedom for quantum entanglement within tensor networks can enhance the depiction of the essence in many-body systems. However, this enhancement comes with a significant increase in computational complexity and critical slowing down, which drastically increases time consumption. This work converts a quantum tensor network algorithm into a classical circuit on the Field Programmable Gate Arrays (FPGAs) and arranges the computing unit with a dense parallel design, efficiently optimizing the time consumption. Test results show that the FPGA-based design achieves a computational speed 1.7 times greater than that of the central processing unit and is comparable to the graphics processing unit. This work explores a scalable and reusable approach suitable for parallel tensor operations implemented on FPGA, advancing research in quantum physics for many-body computing and quantum technologies.

Review of Scientific Instruments•Jan 1, 2025•1 citation

Tree Tensor Network implemented on FPGA as ultra-low latency binary classifiers.

Lorenzo Borella, Alberto Coppi, J. Pazzini +3 more

Tensor Networks (TNs) are a computational framework traditionally used to model quantum many-body systems. Recent research has demonstrated that TNs can also be effectively applied to Machine Learning (ML) tasks, producing results comparable to conventional supervised learning methods. In this work, we investigate the use of Tree Tensor Networks (TTNs) for high-frequency real-time applications by harnessing the low-latency capabilities of Field-Programmable Gate Arrays (FPGAs). We present the implementation of TTN classifiers on FPGA hardware, optimized for performing inference on classical ML benchmarking datasets. Various degrees of parallelization are explored to evaluate the trade-offs between resource utilization and algorithm latency. By deploying these TTNs on a hardware accelerator and utilizing an FPGA integrated into a server, we fully offload the TTN inference process, demonstrating the system’s viability for real-time ML applications.

International Conference on High Energy Physics (ICHEP)•Jan 27, 2025•0 citations

Implementation of Tensor Network Simulation TN-Sim under NWQ-Sim

Aaron C. Hoyt, Jonathan S. Bersson, Sean Garner +2 more

Large-scale tensor network simulations are crucial for developing robust complexity-theoretic bounds on classical quantum simulation, enabling circuit cutting approaches, and optimizing circuit compilation, all of which aid efficient quantum computation on limited quantum resources. Modern exascale high-performance computing platforms offer significant potential for advancing tensor network quantum circuit simulation capabilities. We implement TN-Sim, a tensor network simulator backend within the NWQ-Sim software package that utilizes the Tensor Algebra for Many-body Methods (TAMM) framework to support both distributed HPC-scale computations and local simulations with ITensor. To optimize the scale up in computation across multiple nodes we implement a task based parallelization scheme to demonstrate parallelized gate contraction for wide quantum circuits with many gates per layer. Through the integration of the TAMM framework with Matrix Product State (MPS) tensor network approaches, we deliver a simulation environment that can scale from local systems to HPC clusters. We demonstrate an MPS tensor network simulator running on the state-of-the-art Perlmutter (NVIDIA) supercomputer and discuss the potential portability of this software to HPC clusters such as Frontier (AMD) and Aurora (Intel). We also discuss future improvements including support for different tensor network topologies and enhanced computational efficiency.

quant-pharXiv:2601.04422•IEEE High Performance Extreme Computing Conference•Jan 9, 2026•0 citations

Towards an Efficiently Simulated Quantum Approximate Optimisation

Amir Alizadeh, Amir Pourabdollah, Ahmad Lotfi

Many large-scale optimisation problems, such as those in power systems, finance and logistics can be potentially solved in the fundamentally new approach of quantum algorithms, namely Quantum Approximate Optimisation Algorithm (QAOA). In the context of fuzzy systems for instance, it is already shown that some of the intense computation associated with complex or higher-order fuzzy logic systems can be offloaded to such quantum algorithms. While the quantum computation hardware technology is still in its infancy, efficient simulations of the quantum algorithms play a crucial role in advancing quantum algorithms. The current CPU/GPU-based approaches suffer from high energy consumption and speed and scalability limitations. This paper presents the current position of our research to develop an efficient and scalable QAOA simulation based on a large network of Field-Programmable Gate Array (FPGA) modules, inspired by FPGA’s hardware-level parallelism. Although there exist a few attempts on using FPGA for general quantum circuits simulation, this project introduces a novel approach by employing a highly efficient recursive matrix decomposition algorithms specifically designed for QAOA. This work can pave the pathway a scalable and energy-efficient solution for cross-domain optimisation problems. The actual results and evaluations are to be reported in follow-up publications.

IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)•Jul 6, 2025•0 citations

Relational Quantum Circuit Compilation via Tensor Networks

Jincheng Zhang

Quantum circuit compilation is a critical step in realizing quantum computation, aiming to translate high-level quantum algorithms into a sequence of low-level gate operations executable on a quantum hardware. Traditional compilation methods often suffer from exponential scaling in the representation of the quantum state space, leading to prohibitive computational costs. This work introduces a novel approach to quantum circuit compilation utilizing tensor networks. We represent quantum circuits and their resulting states as higher-order tensor networks, enabling efficient manipulation and contraction of these representations. Our algorithm leverages tensor contraction and permutation techniques specifically tailored to the inherent structure of quantum circuits, minimizing the rank of the tensor networks and, consequently, reducing computational overhead. This approach offers the potential for significant speedups compared to conventional compilation techniques, addressing the core challenge of exponential scaling in quantum state representation. The method's effectiveness is demonstrated through theoretical analysis and a novel compilation algorithm.

•Sep 3, 2026•0 citations

Improving the computational efficiency of quantum many-body calculations from a hardware perspective remains a critical challenge. Although field-programmable gate arrays (FPGAs) have recently been exploited to improve the computational scaling of algorithms such as Monte Carlo methods, their application to tensor network algorithms is still at an early stage. In this work, we propose a fine-grained parallel tensor network design based on FPGAs to substantially enhance the computational efficiency of two representative tensor network algorithms: the infinite time-evolving block decimation (iTEBD) and the higher-order tensor renormalization group (HOTRG). By employing a quad-tile partitioning strategy to decompose tensor elements and map them onto hardware circuits, our approach effectively translates algorithmic computational complexity into scalable hardware resource utilization, enabling an extremely high degree of parallelism on FPGAs. Compared with conventional CPU-based implementations, our scheme exhibits superior scalability in computation time, reducing the bond-dimension scaling of the computational cost from

O(D_b^3)

to

O(D_b)

for iTEBD and from

O(D_b^6)

to

O(D_b^2)

for HOTRG. This work provides a theoretical foundation for future hardware implementations of large-scale tensor network computations.

Abstract A new implementation of many-body calculations is of paramount importance in the field of computational physics. In this study, we leverage the capabilities of Field Programmable Gate Arrays (FPGAs) for conducting quantum many-body calculations. Through the design of appropriate schemes for Monte Carlo and tensor network methods, we effectively utilize the parallel processing capabilities provided by FPGAs. This has resulted in a remarkable tenfold speedup compared to CPU-based computation for a Monte Carlo algorithm. We also demonstrate, for the first time, the utilization of FPGA to accelerate a typical tensor network algorithm. Our findings unambiguously highlight the significant advantages of hardware implementation and pave the way for novel approaches to many-body calculations.

Increasing the degree of freedom for quantum entanglement within tensor networks can enhance the depiction of the essence in many-body systems. However, this enhancement comes with a significant increase in computational complexity and critical slowing down, which drastically increases time consumption. This work converts a quantum tensor network algorithm into a classical circuit on the Field Programmable Gate Arrays (FPGAs) and arranges the computing unit with a dense parallel design, efficiently optimizing the time consumption. Test results show that the FPGA-based design achieves a computational speed 1.7 times greater than that of the central processing unit and is comparable to the graphics processing unit. This work explores a scalable and reusable approach suitable for parallel tensor operations implemented on FPGA, advancing research in quantum physics for many-body computing and quantum technologies.

Tensor Networks (TNs) are a computational framework traditionally used to model quantum many-body systems. Recent research has demonstrated that TNs can also be effectively applied to Machine Learning (ML) tasks, producing results comparable to conventional supervised learning methods. In this work, we investigate the use of Tree Tensor Networks (TTNs) for high-frequency real-time applications by harnessing the low-latency capabilities of Field-Programmable Gate Arrays (FPGAs). We present the implementation of TTN classifiers on FPGA hardware, optimized for performing inference on classical ML benchmarking datasets. Various degrees of parallelization are explored to evaluate the trade-offs between resource utilization and algorithm latency. By deploying these TTNs on a hardware accelerator and utilizing an FPGA integrated into a server, we fully offload the TTN inference process, demonstrating the system’s viability for real-time ML applications.

Large-scale tensor network simulations are crucial for developing robust complexity-theoretic bounds on classical quantum simulation, enabling circuit cutting approaches, and optimizing circuit compilation, all of which aid efficient quantum computation on limited quantum resources. Modern exascale high-performance computing platforms offer significant potential for advancing tensor network quantum circuit simulation capabilities. We implement TN-Sim, a tensor network simulator backend within the NWQ-Sim software package that utilizes the Tensor Algebra for Many-body Methods (TAMM) framework to support both distributed HPC-scale computations and local simulations with ITensor. To optimize the scale up in computation across multiple nodes we implement a task based parallelization scheme to demonstrate parallelized gate contraction for wide quantum circuits with many gates per layer. Through the integration of the TAMM framework with Matrix Product State (MPS) tensor network approaches, we deliver a simulation environment that can scale from local systems to HPC clusters. We demonstrate an MPS tensor network simulator running on the state-of-the-art Perlmutter (NVIDIA) supercomputer and discuss the potential portability of this software to HPC clusters such as Frontier (AMD) and Aurora (Intel). We also discuss future improvements including support for different tensor network topologies and enhanced computational efficiency.

Many large-scale optimisation problems, such as those in power systems, finance and logistics can be potentially solved in the fundamentally new approach of quantum algorithms, namely Quantum Approximate Optimisation Algorithm (QAOA). In the context of fuzzy systems for instance, it is already shown that some of the intense computation associated with complex or higher-order fuzzy logic systems can be offloaded to such quantum algorithms. While the quantum computation hardware technology is still in its infancy, efficient simulations of the quantum algorithms play a crucial role in advancing quantum algorithms. The current CPU/GPU-based approaches suffer from high energy consumption and speed and scalability limitations. This paper presents the current position of our research to develop an efficient and scalable QAOA simulation based on a large network of Field-Programmable Gate Array (FPGA) modules, inspired by FPGA’s hardware-level parallelism. Although there exist a few attempts on using FPGA for general quantum circuits simulation, this project introduces a novel approach by employing a highly efficient recursive matrix decomposition algorithms specifically designed for QAOA. This work can pave the pathway a scalable and energy-efficient solution for cross-domain optimisation problems. The actual results and evaluations are to be reported in follow-up publications.

Quantum circuit compilation is a critical step in realizing quantum computation, aiming to translate high-level quantum algorithms into a sequence of low-level gate operations executable on a quantum hardware. Traditional compilation methods often suffer from exponential scaling in the representation of the quantum state space, leading to prohibitive computational costs. This work introduces a novel approach to quantum circuit compilation utilizing tensor networks. We represent quantum circuits and their resulting states as higher-order tensor networks, enabling efficient manipulation and contraction of these representations. Our algorithm leverages tensor contraction and permutation techniques specifically tailored to the inherent structure of quantum circuits, minimizing the rank of the tensor networks and, consequently, reducing computational overhead. This approach offers the potential for significant speedups compared to conventional compilation techniques, addressing the core challenge of exponential scaling in quantum state representation. The method's effectiveness is demonstrated through theoretical analysis and a novel compilation algorithm.