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International Conference on High Energy Physics (ICHEP)

Tree Tensor Network implemented on FPGA as ultra-low latency binary classifiers.

Lorenzo Borella, Alberto Coppi, J. Pazzini, Andrea Stanco, Andrea Triossi, M. Zanetti

Published Jan 27, 2025• 0 citations
Publisher

Abstract

Tensor Networks (TNs) are a computational framework traditionally used to model quantum many-body systems. Recent research has demonstrated that TNs can also be effectively applied to Machine Learning (ML) tasks, producing results comparable to conventional supervised learning methods. In this work, we investigate the use of Tree Tensor Networks (TTNs) for high-frequency real-time applications by harnessing the low-latency capabilities of Field-Programmable Gate Arrays (FPGAs). We present the implementation of TTN classifiers on FPGA hardware, optimized for performing inference on classical ML benchmarking datasets. Various degrees of parallelization are explored to evaluate the trade-offs between resource utilization and algorithm latency. By deploying these TTNs on a hardware accelerator and utilizing an FPGA integrated into a server, we fully offload the TTN inference process, demonstrating the system’s viability for real-time ML applications.

DOI
10.22323/1.476.1004

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Tensor Networks (TNs) are a computational framework traditionally used to model quantum many-body systems. Recent research has demonstrated that TNs can also be effectively applied to Machine Learning (ML) tasks, producing results comparable to conventional supervised learning methods. In this work, we investigate the use of Tree Tensor Networks (TTNs) for high-frequency real-time applications by harnessing the low-latency capabilities of Field-Programmable Gate Arrays (FPGAs). We present the implementation of TTN classifiers on FPGA hardware, optimized for performing inference on classical ML benchmarking datasets. Various degrees of parallelization are explored to evaluate the trade-offs between resource utilization and algorithm latency. By deploying these TTNs on a hardware accelerator and utilizing an FPGA integrated into a server, we fully offload the TTN inference process, demonstrating the system’s viability for real-time ML applications.
Abstract Tensor networks (TNs) are a computational paradigm used for representing quantum many-body systems. Recent works have shown how TNs can also be applied to perform machine learning (ML) tasks, yielding comparable results to standard supervised learning techniques. In this work, we study the use of Tree TNs (TTNs) in high-frequency real-time applications by exploiting the low-latency hardware of the field-programmable gate array (FPGA) technology. We present different implementations of TTN classifiers, capable of performing inference on classical ML datasets as well as on complex physics data. A preparatory analysis of bond dimensions and weight quantization is realized in the training phase, together with entanglement entropy and correlation measurements, that help setting the choice of the TTN architecture. The generated TTNs are then deployed on a hardware accelerator; using an FPGA integrated into a server, the inference of the TTN is completely offloaded. Eventually, a classifier for high energy physics applications is implemented and executed fully pipelined with sub-microsecond latency.
We present a systematic study of Tensor Network (TN) models $\unicode{x2013}$ Matrix Product States (MPS) and Tree Tensor Networks (TTN) $\unicode{x2013}$ for real-time jet tagging in high-energy physics, with a focus on low-latency deployment on Field Programmable Gate Arrays (FPGAs). Motivated by the strict requirements of the HL-LHC Level-1 trigger system, we explore TNs as compact and interpretable alternatives to deep neural networks. Using low-level jet constituent features, our models achieve competitive performance compared to state-of-the-art deep learning classifiers. We investigate post-training quantization to enable hardware-efficient implementations without degrading classification performance or latency. The best-performing models are synthesized to estimate FPGA resource usage, latency, and memory occupancy, demonstrating sub-microsecond latency and supporting the feasibility of online deployment in real-time trigger systems. Overall, this study highlights the potential of TN-based models for fast and resource-efficient inference in low-latency environments.
Abstract A new implementation of many-body calculations is of paramount importance in the field of computational physics. In this study, we leverage the capabilities of Field Programmable Gate Arrays (FPGAs) for conducting quantum many-body calculations. Through the design of appropriate schemes for Monte Carlo and tensor network methods, we effectively utilize the parallel processing capabilities provided by FPGAs. This has resulted in a remarkable tenfold speedup compared to CPU-based computation for a Monte Carlo algorithm. We also demonstrate, for the first time, the utilization of FPGA to accelerate a typical tensor network algorithm. Our findings unambiguously highlight the significant advantages of hardware implementation and pave the way for novel approaches to many-body calculations.
Improving the computational efficiency of quantum many-body calculations from a hardware perspective remains a critical challenge. Although field-programmable gate arrays (FPGAs) have recently been exploited to improve the computational scaling of algorithms such as Monte Carlo methods, their application to tensor network algorithms is still at an early stage. In this work, we propose a fine-grained parallel tensor network design based on FPGAs to substantially enhance the computational efficiency of two representative tensor network algorithms: the infinite time-evolving block decimation (iTEBD) and the higher-order tensor renormalization group (HOTRG). By employing a quad-tile partitioning strategy to decompose tensor elements and map them onto hardware circuits, our approach effectively translates algorithmic computational complexity into scalable hardware resource utilization, enabling an extremely high degree of parallelism on FPGAs. Compared with conventional CPU-based implementations, our scheme exhibits superior scalability in computation time, reducing the bond-dimension scaling of the computational cost from O(Db3)O(D_b^3)O(Db3​) to O(Db)O(D_b)O(Db​) for iTEBD and from O(Db6)O(D_b^6)O(Db6​) to O(Db2)O(D_b^2)O(Db2​) for HOTRG. This work provides a theoretical foundation for future hardware implementations of large-scale tensor network computations.
We describe a quantum-assisted machine learning method in which multivariate data are encoded into quantum states in a Hilbert space whose dimension is exponentially large in the length of the data vector. Learning in this space occurs through applying a low-depth quantum circuit with a tree-tensor-network (TTN) topology acting as an unsupervised feature extractor to identify the most relevant quantum states in a data-driven fashion and then applying a supervised linear classifier encoding the class decision in a small-dimensional quantum register. We present tools for making TTN classifiers amenable to implementation on gate-based quantum computing devices, including an embedding map with accuracy similar to the recently defined exponential machines (A. Novikov et al., arXiv:1605.03795) but which produces valid quantum state embeddings of classical data vectors, and the use of manifold-based gradient optimization schemes to produce isometric operations mapping quantum states to a register of qubits defining a class decision. We detail methods for efficiently obtaining one-point and two-point correlation functions of the vectors defining the decision boundary of the quantum model, which can be used for model interpretability, as well as methods for obtaining classification decisions from partial data vectors. Further, we show that the use of isometric tensors can significantly aid in the human interpretability of the correlation functions extracted from the decision weights and may produce models that are less susceptible to adversarial perturbations. Finally, we discuss in detail the problem of compiling classically optimized isometric TTN models into unitary operations to be run on quantum computers and how isometric models requiring postselection on quantum hardware can be used to precondition variational Ans\"atze for models without postselection. We demonstrate our methodologies in applications utilizing the MNIST database of handwritten digits and a multivariate time-series data set of human activity recognition.
Measuring a qubit state is a fundamental yet error-prone operation in quantum computing. These errors can arise from various sources, such as crosstalk, spontaneous state transitions, and excitations caused by the readout pulse. Here, we utilize an integrated approach to deploy neural networks onto field-programmable gate arrays (FPGA). We demonstrate that implementing a fully connected neural network accelerator for multi-qubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. The neural network is implemented by quantizing weights, activation functions, and inputs. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in less than 50 ns on a radio frequency system on chip (RFSoC) ZCU111 FPGA, marking the advent of RFSoC-based low-latency multi-qubit readout using neural networks. These modules can be implemented and integrated into existing quantum control and readout platforms, making the RFSoC ZCU111 ready for experimental deployment.