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arXiv:2512.03588

Numerical simulation of coherent spin-shuttling in a QuBus with charged defects

Nils Ciroth, Arnau Sala, Ran Xue, Lasse Ermoneit, Thomas Koprucki, Markus Kantner, Lars R. Schreiber

cond-mat.mes-hallquant-phSubmitted Dec 3, 2025• Announced Dec 4, 2025
arXivHTMLPDF

Abstract

Recent advances in coherent conveyor-mode spin qubit shuttling are paving the way for large-scale quantum computing platforms with qubit connectivity achieved by spin qubit shuttles. We developed a simulation tool to investigate numerically the impact of device imperfections on the spin-coherence of conveyor-mode shuttling in Si/SiGe. We simulate the quantum evolution of a mobile electron spin-qubit under the influence of sparse and singly charged point defects placed in the Si/SiGe heterostructure in close proximity to the shuttle lane. We consider different locations of a single charge defect with respect to the center of the shuttle lane, multiple orbital states of the electron in the shuttle with $g$-factor differences between the orbital levels, and orbital relaxation induced by electron-phonon interaction. With this simulation framework, we identify the critical defect density of charged point defects in the heterostructure for conveyor-mode spin qubit shuttle devices and quantify the impact of a single defect on the coherence of a qubit.

Journal reference
Phys. Rev. B 114, 105305 (2026)
DOI
10.1103/styv-ypg9

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Recent advances in coherent conveyor-mode spin qubit shuttling are paving the way for large-scale quantum computing platforms with qubit connectivity achieved by spin qubit shuttles. We developed a simulation tool to investigate numerically the impact of device imperfections on the spin-coherence of conveyor-mode shuttling in Si/SiGe. We simulate the quantum evolution of a mobile electron spin-qubit under the influence of sparse and singly charged point defects placed in the Si/SiGe heterostructure in close proximity to the shuttle lane. We consider different locations of a single charge defect with respect to the center of the shuttle lane, multiple orbital states of the electron in the shuttle with ggg-factor differences between the orbital levels, and orbital relaxation induced by electron-phonon interaction. With this simulation framework, we identify the critical defect density of charged point defects in the heterostructure for conveyor-mode spin qubit shuttle devices and quantify the impact of a single defect on the coherence of a qubit.
Extensive theoretical and experimental work has established high-fidelity electron shuttling in Si/SiGe systems, whereas demonstrations in Si/SiO2, also known as silicon metal-oxide-semiconductor (SiMOS), devices remain at an early stage. To help address this, we perform full 3D simulations of conveyor-belt charge shuttling in a realistic SiMOS device, building on earlier 2D modelling. We solve the Poisson and time-dependent Schrodinger equations for varying shuttling speeds and gate voltages, focusing on potential pitfalls of typical SiMOS devices such as oxide-interface roughness, gate fabrication imperfections, and charge defects along the transport path. The simulations reveal that for low clavier-gate voltages, the additional oxide screening in multi-layer gate architectures causes conveyor-belt shuttling to collapse to the bucket-brigade mode, inducing considerable orbital excitation in the process. Increasing the confinement restores conveyor-belt operation, which we find to be robust against interface roughness, gate misalignment, and charge defects buried in the oxide. However, our results indicate that defects located at the Si/SiO2-interface can induce considerable orbital excitation. For lower conveyor gate biases, positive defects in the transport channel can even capture passing electrons. Hence we identify key challenges and find operating regimes for reliable charge transport in SiMOS architectures.
Long-ranged coherent qubit coupling is a missing function block for scaling up spin qubit based quantum computing solutions. Spin-coherent conveyor-mode electron-shuttling could enable spin quantum-chips with scalable and sparse qubit-architecture. Its key feature is the operation by only few easily tuneable input terminals and compatibility with industrial gate-fabrication. Single electron shuttling in conveyor-mode in a 420 nm long quantum bus has been demonstrated previously. Here we investigate the spin coherence during conveyor-mode shuttling by separation and rejoining an Einstein-Podolsky-Rosen (EPR) spin-pair. Compared to previous work we boost the shuttle velocity by a factor of 10000. We observe a rising spin-qubit dephasing time with the longer shuttle distances due to motional narrowing and estimate the spin-shuttle infidelity due to dephasing to be 0.7% for a total shuttle distance of nominal 560 nm. Shuttling several loops up to an accumulated distance of 3.36 μm, spin-entanglement of the EPR pair is still detectable, giving good perspective for our approach of a shuttle-based scalable quantum computing architecture in silicon.
Mobile spin qubit architectures promise flexible connectivity for efficient quantum error correction and relaxed device layout constraints, but their viability rests on preserving spin coherence during transport. While shuttling transforms spatial disorder into time-dependent noise, its net impact on spin coherence remains an open question. Here we demonstrate systematic noise mitigation during spin shuttling in a linear 28^{28}28Si/SiGe quantum dot device. First, by passively reducing magnetic field gradients, we minimize charge-noise coupling to the spin and double the spatially averaged dephasing time T2∗(xn)T_2^*(x_n)T2∗​(xn​) from 4.44.44.4 to 8.5 μs8.5\,μ\text{s}8.5μs. Next, we exploit motional narrowing by periodically shuttling the qubit, achieving a further enhancement in coherence time up to T2∗,sh=11.5 μsT_{2}^{*,sh} = 11.5\,μ\text{s}T2∗,sh​=11.5μs. Finally, we incorporate dynamical decoupling techniques while periodically shuttling over distances exceeding 200 nm200\,\text{nm}200nm, reaching T2H,sh=32 μsT_\text{2}^{H,sh}= 32\,μ\text{s}T2H,sh​=32μs. For the same setup, we demonstrate that dressed-state shuttling provides robust protection against low-frequency noise with a decay time TRsh=21 μsT_R^{\text{sh}} = 21\,μ\text{s}TRsh​=21μs, without the overhead of pulsed control and allowing protection during one-way spin transport. By preserving coherence over timescales exceeding typical gate and readout operations, the demonstrated strategies establish mobile spin qubits as a viable solution for scalable silicon quantum processors.
Universal quantum computing promises solutions to a wide range of problems of significant scientific and socioeconomic impact that are computationally intractable using classical hardware. Since physical qubits are inherently noisy and prone to decoherence, realizing a sufficient number of logical qubits to unlock practically relevant problem classes will likely require quantum error correction, resulting in an overhead of millions of physical qubits. Among all competing hardware platforms, spin qubits in gate-defined quantum dots are uniquely positioned: single- and two-qubit gate fidelities routinely exceed the error-correction threshold, and the experimentally proven compatibility with industrial-grade semiconductor manufacturing may enable millions of qubits on a single chip. Realizing this potential, however, requires quantum processor architectures that scale to large qubit numbers with two‑dimensional connectivity while maintaining high operational fidelities. Building on the theoretical feasibility of high‑fidelity spin‑coherent electron shuttling, the SpinBus architecture is introduced to enable scaling to application-relevant qubit numbers. The SpinBus architecture leverages the conveyor-mode shuttling device named Quantum Bus (QuBus) for coherent qubit coupling over micron‑scale distances to accommodate, at the level of the quantum processor chip, wiring fan‑out and locally integrated control electronics at cryogenic temperatures. Device simulations for all relevant operations in the Si/SiGe platform validate operation fidelities exceeding 99 % as well as compatibility with the requirements of established semiconductor patterning technology. Control with room‑temperature electronics plausibly supports at least 144 qubits, while substantially larger quantum processor sizes are conceivable using cryogenic control electronics. For the experimental realization of QuBus devices, a novel high‑yield multilayer electron-beam lithography process, which can readily be adapted to different device layouts, was developed to fabricate the required > 100 aligned metallic gate electrodes. Benchmarking with a semiconductor industry‑inspired methodology and inspection of > 100 devices demonstrated 99 % gate fabrication yield and at least 5 nm overlay accuracy. Utilizing GaAs/(Al,Ga)As QuBus prototype devices with a 7 µm shuttling channel for quantized-current experiments validated key criteria for conveyor-mode shuttling, in particular linear current scaling for operation frequencies up to 40 MHz, and provided preliminary evidence consistent with quantized conveyor-mode electron transfer. These results support the viability of conveyor-mode shuttling for qubit coupling and indicate the suitability of QuBus devices for metrological applications.
Conveyor-mode shuttling in gated Si/SiGe devices enables adiabatic transfer of single electrons, electron patterns and spin qubits confined in quantum dots across several microns with a scalable number of signal lines. To realize their full potential, linear shuttle lanes must connect into a two-dimensional grid with controllable routing. We introduce a T-junction device linking two independently driven shuttle lanes. Electron routing across the junction requires no extra control lines beyond the four channels per conveyor belt. We measure an inter-lane charge transfer fidelity of F=100.0000000−9×10−7+0 %F = 100.0000000^{+0}_{-9\times 10^{-7}}\,\%F=100.0000000−9×10−7+0​% at an instantaneous electron velocity of 270 mm s−1270\,\mathrm{mm}\,\mathrm{s}^{-1}270mms−1. The filling of 54 quantum dots is controlled by simple atomic pulses, allowing us to swap electron patterns, laying the groundwork for a native spin-qubit SWAP gate. This T-junction establishes a path towards scalable, two-dimensional quantum computing architectures with flexible spin qubit routing for quantum error correction.
Abstract Small spin-qubit registers defined by single electrons confined in Si/SiGe quantum dots operate successfully and connecting these would permit scalable quantum computation. Shuttling the qubit carrying electrons between registers is a natural choice for high-fidelity coherent links provided the overhead of control signals stays moderate. Our proof-of-principle demonstrates shuttling of a single electron by a propagating wave-potential in an electrostatically defined 420 nm long Si/SiGe quantum-channel. This conveyor-mode shuttling approach requires independent from its length only four sinusoidal control signals. We discuss the tuning of the signal parameters, detect the smoothness of the electron motion enabling the mapping of potential disorder and observe a high single-electron shuttling fidelity of 99.42 ± 0.02% including a reversal of direction. Our shuttling device can be readily embedded in industrial fabrication of Si/SiGe qubit chips and paves the way to solving the signal-fanout problem for a fully scalable semiconductor quantum-computing architecture.