Chiplet technology for large-scale trapped-ion quantum processors
Bassem Badawi, Philip C. Holz, Michael Raffetseder, Nicolas Jungwirth, Juris Ulmanis, Hans-Joachim Quenzer, Dirk Kähler, Thomas Monz, Philipp Schindler
quant-phSubmitted Dec 2, 2025• Announced Dec 3, 2025• 1 citation
Trapped ions are among the most promising platforms for realizing a large-scale quantum information processor. Current progress focuses on integrating optical and electronic components into microfabricated ion traps to allow scaling to large numbers of ion qubits. Most available fabrication strategies for such integrated processors employ monolithic integration of all processor components and rely heavily on CMOS-compatible semiconductor fabrication technologies that are not optimized for the requirements of a trapped-ion quantum processor. In this work, we present a modular approach in which the processor modules, called chiplets, have specific functions and are fabricated separately. The individual chiplets are then combined using heterogeneous integration techniques. This strategy opens up the possibility of choosing the optimal materials and fabrication technology for each of the chiplets, with a minimum amount of fabrication limitations compared to the monolithic approach. Chiplet technology furthermore enables novel processor functionalities to be added in a cost-effective, modular fashion by adding or modifying only a subset of the chiplets. We describe the design concept of a chiplet-based trapped-ion quantum processor and demonstrate the technology with an example of an integrated individual-ion addressing system for a ten-ion crystal. The addressing system emphasizes the modularity of the chiplet approach, combining a surface ion trap manufactured on a glass substrate with a silicon substrate carrying integrated waveguides and a stack of 3D-printed micro-optics, achieving diffraction-limited focal spots at the ion positions.
Trapped ions are among the most promising platforms for realizing a large-scale quantum information processor. Current progress focuses on integrating optical and electronic components into microfabricated ion traps to allow scaling to large numbers of ion qubits. Most available fabrication strategies for such integrated processors employ monolithic integration of all processor components and rely heavily on CMOS-compatible semiconductor fabrication technologies that are not optimized for the requirements of a trapped-ion quantum processor. In this work, we present a modular approach in which the processor modules, called chiplets, have specific functions and are fabricated separately. The individual chiplets are then combined using heterogeneous integration techniques. This strategy opens up the possibility of choosing the optimal materials and fabrication technology for each of the chiplets, with a minimum amount of fabrication limitations compared to the monolithic approach. Chiplet technology furthermore enables novel processor functionalities to be added in a cost-effective, modular fashion by adding or modifying only a subset of the chiplets. We describe the design concept of a chiplet-based trapped-ion quantum processor and demonstrate the technology with an example of an integrated individual-ion addressing system for a ten-ion crystal. The addressing system emphasizes the modularity of the chiplet approach, combining a surface ion trap manufactured on a glass substrate with a silicon substrate carrying integrated waveguides and a stack of 3D-printed micro-optics, achieving diffraction-limited focal spots at the ion positions.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
A design is proposed for a novel ion trap quantum processor chip, microfabricated using a process based on planar silica-on-silicon techniques. The trap electrodes are of gold-coated silica and are spaced by highly doped silicon in a monolithic structure. This design allows a unit aspect-ratio trap with an ion-electrode separation below 100 μm, when using current fabrication techniques. The trapping potential is modelled and the operating parameters required to achieve motional frequencies of a few MHz are calculated. RF loss and the resultant heating of the trap chip are not found to be a factor limiting the trap's operation. This monolithic unit aspect-ratio trap is therefore expected to exhibit a deep potential well, high trap efficiency, and a low RF loss, when compared to other microfabricated traps. This technological approach is in principle scaleable to complex devices, and may form the basis for large-scale ion trap quantum processors.
Integrated optical control of trapped-ion qubits leveraging dielectric waveguides photonics within planar-fabricated trap devices offers routes to scaling the optical control critical to trapped-ion quantum computing. The ultraviolet to infrared functionality required for many atomic systems, the multiple metal layers for large-scale trap arrays, and the long-term interest in integration of active functionality and integrated electronics motivates development of foundry-based platforms for such systems, to facilitate accessibility to the complex fabrication involved. Aside from scaling, utilization of such technology in trapped-ion quantum systems further stands to alleviate limitations on basic physical operations employed in both quantum computing and metrology, which experiments are starting to demonstrate. I will summarize our recent results using phase-stable standing-wave delivery practically enabled by integrated photonic addressing to enhance ground-state laser cooling, which we experimentally demonstrate using trap devices with integrated Al2O3 and Si3N4 waveguides for UV-NIR addressing fabricated in a commercial foundry. I will also discuss relevance of similar ideas to alleviating power requirements in laser-based entangling gates, and work in progress towards experimental realization, including in a 300 mm-wafer foundry platform for such devices in development.
Abstract: This study investigates photonic-interconnected quantum chiplets as a modular hardware pathway for scalable and networked quantum computing. The central problem is that monolithic quantum processors face compounding constraints in yield, wiring density, cryogenic routing, interconnect loss, calibration complexity and non-local connectivity. Photonic interconnection offers a technically plausible route to divide a large quantum computer into smaller processors while preserving quantum communication across modules through fibre links, photonic switches, optical transduction or integrated photonic interposers. The paper develops an academically rigorous framework that connects quantum-chiplet architecture, photonic integration, quantum error correction, control latency and manufacturability. It uses secondary real-data anchors from recent public demonstrations and a transparent engineering analysis to evaluate whether modular photonic networking can satisfy requirements for distributed logical qubits, entanglement generation and fault-tolerant operation. Results indicate that photonic chiplets can reduce scaling penalties relative to a monolithic wiring strategy when interconnect loss, feed-forward latency and module yield are jointly optimized. The study concludes that photonic-interconnected chiplets are not a minor packaging improvement but a possible architectural transition comparable to the movement from single-die classical processors to heterogeneous chiplet systems. The strongest contribution is a system-level evaluation model that links physical photonic performance with computer-architecture metrics and identifies the practical thresholds that must be met for Nature-level experimental validation. Keywords quantum computing chips, photonic chiplets, modular quantum computing, quantum interconnects, distributed quantum processors, silicon photonics, quantum networking, fault-tolerant quantum computing, optical interposers, quantum error correction, entanglement routing, wafer-scale quantum manufacturing, cryogenic control, quantum architecture, quantum hardware scalability
Surface electrode ion trap is a promising candidate for quantum information processing (QIP), due to its feasibilities towards large-scale fabrication and on-chip electro-optical integration. In this paper, surface electrode ion traps on different substrates (e.g., high-resistivity silicon, silicon with ground plane and glass) are fabricated, assembled and tested. To simultaneously leverage the established fabrication technique of silicon and superior insulation property of glass, we further demonstrate a novel ion trap design with heterogenous integration of silicon and glass, acting respectively as ion trap and interposer substrates. The vertical connection between the silicon ion trap and the glass interposer is achieved by through silicon via (TSV) and micro bump. This silicon-glass integrated system advances the development of ion trap and enriches the toolbox of scalable QIP.
Abstract Ion traps are used for a wide range of applications from metrology to quantum simulations and quantum information processing. Microfabricated chip-based 3D ion traps are scalable to store many ions for the realization of a large number of qubits, provide deep trapping potentials compared to surface traps, and very good shielding from external electric fields. In this work, we give an overview of our recent developments on chip-based 3D ion traps. Different types of chip materials, the integration of electronic filter components on-chip and compact electrical connections in vacuum are discussed. Further, based on finite element method simulations, we discuss how integrating micro-optics in 3D ion traps is possible without disturbing the trapped ions.