We introduce an ion trap platform based on a 3D-printed micro-junction array, designed to implement quantum charge-coupled device (QCCD) architectures for large-scale quantum information processing (QIP). The integration of three-dimensionally structured micro Radio-Frequency (RF) electrodes above a surface-electrode trap enables flexible control of electric field profiles across both linear and junction regions. Through simulations, we demonstrate that the linear region exhibits deeper and more harmonic ion confinement with reduced RF drive power compared to conventional planar traps. Crucially, we identify a junction geometry that maintains uniform ion confinement during transport while substantially reducing the pseudopotential barrier. This reduction facilitates low-heating, high-fidelity transport of single- and multi-species ion crystals. Our results establish a viable route toward fault-tolerant quantum computing by enabling modular and scalable QCCD systems based on the state-of-the-art 3D-printing technologies.
We introduce an ion trap platform based on a 3D-printed micro-junction array, designed to implement quantum charge-coupled device (QCCD) architectures for large-scale quantum information processing (QIP). The integration of three-dimensionally structured micro Radio-Frequency (RF) electrodes above a surface-electrode trap enables flexible control of electric field profiles across both linear and junction regions. Through simulations, we demonstrate that the linear region exhibits deeper and more harmonic ion confinement with reduced RF drive power compared to conventional planar traps. Crucially, we identify a junction geometry that maintains uniform ion confinement during transport while substantially reducing the pseudopotential barrier. This reduction facilitates low-heating, high-fidelity transport of single- and multi-species ion crystals. Our results establish a viable route toward fault-tolerant quantum computing by enabling modular and scalable QCCD systems based on the state-of-the-art 3D-printing technologies.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
Abstract Junctions are fundamental elements that support qubit locomotion in two-dimensional ion trap arrays and enhance connectivity in emerging trapped-ion quantum computers. In surface ion traps they have typically been implemented by shaping radio frequency (RF) electrodes in a single plane to minimize the disturbance to the pseudopotential. However, this method introduces issues related to RF lead routing that can increase power dissipation and the likelihood of voltage breakdown. Here, we propose and simulate a novel two-layer junction design incorporating two perpendicularly rotoreflected (rotated, then reflected) linear ion traps. The traps are vertically separated, and create a trapping potential between their respective planes. The orthogonal orientation of the RF electrodes of each trap relative to the other provides perpendicular axes of confinement that can be used to realize transport in two dimensions. While this design introduces manufacturing and operating challenges, as now two separate structures have to be precisely positioned relative to each other in the vertical direction and optical access from the top is obscured, it obviates the need to route RF leads below the top surface of the trap and eliminates the pseudopotential bumps that occur in typical junctions. In this paper the stability of idealized ion transfer in the new configuration is demonstrated, both by solving the Mathieu equation analytically to identify the stable regions and by numerically modeling ion dynamics. Our novel junction layout has the potential to enhance the flexibility of microfabricated ion trap control to enable large-scale trapped-ion quantum computing.
Trapped-ion applications, such as in quantum information, precision measurements, optical clocks, and mass spectrometry, rely on specialized high-performance ion traps. The latter applications typically employ traditional machining to customize macroscopic 3D Paul traps, while quantum information processing experiments usually rely on photo-lithographic techniques to miniaturize the traps and meet scalability requirements. Using photolithography, however, it is challenging to fabricate the complex three-dimensional electrode structures required for optimal confinement. Here we address these limitations by adopting a high-resolution 3D printing technology based on two-photon polymerization supporting fabrication of large arrays of high-performance miniaturized 3D traps. We show that 3D-printed ion traps combine the advantages of traditionally machined 3D traps with the miniaturization provided by photolithography by confining single calcium ions in a small 3D-printed ion trap with radial trap frequencies ranging from 2 MHz to 24 MHz. The tight confinement eases ion cooling requirements and allows us to demonstrate high-fidelity coherent operations on an optical qubit after only Doppler cooling. With 3D printing technology, the design freedom is drastically expanded without sacrificing scalability and precision so that ion trap geometries can be optimized for higher performance and better functionality.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Surface ion traps with two-dimensional layouts of trapping regions are natural architectures for storing large numbers of ions and supporting the connectivity needed to implement quantum algorithms. Many of the components and operations needed to fully exploit this architecture have already been demonstrated, including operation at cryogenic temperatures with low heating, low excitation transport, and ion control and detection with integrated photonics. Here we demonstrate a trap that addresses the scaling challenge of increasing power dissipation as the RF electrode increases in size. By raising the RF electrode and removing most of the insulating dielectric layer below it we reduce both ohmic and dielectric power dissipation. We also measure heating rates across a range of motional frequencies and for different voltage sources in a trap with a raised RF electrode but solid dielectric.
Abstract Trapped ions in radio-frequency traps are among the leading approaches for realizing quantum computers, because of high-fidelity quantum gates and long coherence times1–3. However, the use of radio-frequencies presents several challenges to scaling, including requiring compatibility of chips with high voltages4, managing power dissipation5 and restricting transport and placement of ions6. Here we realize a micro-fabricated Penning ion trap that removes these restrictions by replacing the radio-frequency field with a 3 T magnetic field. We demonstrate full quantum control of an ion in this setting, as well as the ability to transport the ion arbitrarily in the trapping plane above the chip. This unique feature of the Penning micro-trap approach opens up a modification of the quantum charge-coupled device architecture with improved connectivity and flexibility, facilitating the realization of large-scale trapped-ion quantum computing, quantum simulation and quantum sensing.