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arXiv:2504.15725

Low-overhead error detection with spacetime codes

Simon Martiel, Ali Javadi-Abhari

Published Apr 22, 2025• 3 citations
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Abstract

We introduce a low-overhead approach for detecting errors in arbitrary Clifford circuits on arbitrary qubit connectivities. Our method is based on the framework of spacetime codes, and is particularly suited to near-term hardware since it has a much milder overhead in qubits and gates compared to error correction, while achieving a better sampling overhead than existing error mitigation methods. We present efficient algorithms for finding valid checks that are simultaneously low weight, satisfy connectivity constraints, and cover large detecting regions within the circuit. Using this approach, we experimentally demonstrate error detection on circuits of up to 50 logical qubits containing 2450 CZ gates, and show physical to logical fidelity gains of up to $236\times$. Furthermore, we show our algorithm can efficiently find checks in universal circuits, but the space of valid checks diminishes exponentially with the non-Cliffordness of the circuit. These theoretical and experimental results suggest that Clifford-dominated circuits are promising candidates for near-term quantum advantage.

DOI
10.48550/arxiv.2504.15725

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Physical Review Research•Sep 18, 2023•13 citations
We introduce a low-overhead approach for detecting errors in arbitrary Clifford circuits on arbitrary qubit connectivities. Our method is based on the framework of spacetime codes, and is particularly suited to near-term hardware since it has a much milder overhead in qubits and gates compared to error correction, while achieving a better sampling overhead than existing error mitigation methods. We present efficient algorithms for finding valid checks that are simultaneously low weight, satisfy connectivity constraints, and cover large detecting regions within the circuit. Using this approach, we experimentally demonstrate error detection on circuits of up to 50 logical qubits containing 2450 CZ gates, and show physical to logical fidelity gains of up to 236×236\times236×. Furthermore, we show our algorithm can efficiently find checks in universal circuits, but the space of valid checks diminishes exponentially with the non-Cliffordness of the circuit. These theoretical and experimental results suggest that Clifford-dominated circuits are promising candidates for near-term quantum advantage.
Generating samples from the output distribution of a quantum circuit is a ubiquitous task used as a building block of many quantum algorithms. Here we show how to accomplish this task on a noisy quantum processor lacking full-blown error correction for a special class of quantum circuits dominated by Clifford gates. Our approach is based on Coherent Pauli Checks (CPCs) that detect errors in a Clifford circuit by verifying commutation rules between random Pauli-type check operators and the considered circuit. Our main contributions are as follows. First, we derive a simple formula for the probability that a Clifford circuit protected by CPCs contains a logical error. In the limit of a large number of checks, the logical error probability is shown to approach the value ≈7εn/5{\approx}7εn/5≈7εn/5, where nnn is the number of qubits and εεε is the depolarizing error rate. Our formula agrees nearly perfectly with the numerical simulation results. Second, we show that CPCs are well-suited for quantum processors with a limited qubit connectivity. For example, the difference between all-to-all and linear qubit connectivity is only a 3X increase in the number of CNOT gates required to implement CPCs. Third, we describe simplified one-sided CPCs which are well-suited for mitigating measurement errors in the single-shot settings. Finally, we report an experimental demonstration of CPCs with up to 10 logical qubits and more than 100 logical CNOT gates. Our experimental results show that CPCs provide a marked improvement in the logical error probability for the considered task of sampling the output distribution of quantum circuits.
Quantum error correction is essential for building utility-scale quantum computers that outperform classical machines, yet leading approaches incur substantial physical qubit overhead. Quantum low-density parity check (QLDPC) codes offer a promising alternative by significantly reducing the number of physical qubits required per logical qubit. However, existing work on QLDPC codes has focused primarily on quantum memories, with no efficient method known for implementing arbitrary logical Clifford operations at low circuit depth. Here, we introduce a new family of QLDPC codes that enables efficient implementation of the full Clifford group via transversal operations, allowing any m-qubit Clifford operation to be executed in at most O(m) syndrome extraction rounds. We run circuit-level simulations of depth-126 logical circuits to demonstrate the near-memory logical performance of these logical operations. In combination with known methods for implementing T gates, these results establish QLDPC codes as a viable route toward resource-efficient universal quantum computation. Quantum LDPC codes can shield quantum computers from decoherence with minimal overhead. In this work, the authors describe a new QLDPC family, SHYPS, as a path to practical fault tolerance with efficient Clifford circuit implementation on encoded states.
Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling [[n,O(n1/3),O(n1/3)]][[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]][[n,O(n1/3),O(n1/3)]]. In particular, LCS codes realize favorable instances with small numbers of qubits: For the [[15,3,3]][[15,3,3]][[15,3,3]] LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set {H‾i,H‾i,CiXj‾}i,j∈(0,1,2)\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}{Hi​,Hi​,Ci​Xj​​}i,j∈(0,1,2)​ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in d=3d=3d=3 LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range pth≈4.8⋅10−3−1.2⋅10−2p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}pth​≈4.8⋅10−3−1.2⋅10−2 for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.
We propose a Clifford noise reduction (CliNR) scheme that provides a reduction of the logical error rate of Clifford circuit with lower overhead than error correction and without the exponential sampling overhead of error mitigation. CliNR implements Clifford circuits by splitting them into subcircuits that are performed using gate teleportation. A few random stabilizer measurements are used to detect errors in the resources states consumed by the gate teleportation. This can be seen as a teleported version of the coherent parity-check scheme [1-3], with offline fault-detection making it scalable. We prove that CliNR achieves a vanishing logical error rate for families of n-qubit Clifford circuits with size s such that nsp^{2} goes to 0, where p is the physical error rate, meaning that it reaches the regime ns=o(1/p^{2}), whereas the direct implementation is limited to s=o(1/p). Moreover, CliNR uses only 3n+1 qubits, 2s+o(s) gates and has zero rejection rate. This small overhead makes it more practical than quantum error correction in the near term and our numerical simulations show that CliNR provides a reduction of the logical error rate in relevant noise regimes.
Quantum computation promises asymptotic speedups over classical algorithms, but realizing these advantages requires overcoming the noisiness of quantum hardware. Although fault-tolerant error correction can allow for reliable quantum computation even using unreliable components, the resource overheads required can substantially erode the asymptotic performance gains. This dissertation focuses on constructing and optimizing fault-tolerant procedures with lower overhead than previous methods were capable of. We present new frameworks for fault-tolerant syndrome extraction using flag gadgets with exponentially reduced ancilla requirements, explicit measurement schedules that achieve asymptotically fewer measurements than stabilizer generators, and a general method for making arbitrary Clifford circuits fault tolerant. In addition, we optimize surface code measurement schedules in the presence of constraints imposed by fabrication defects to reduce logical error rate. Together, these results advance low-overhead fault tolerance and improve performance in resource-constrained and near-term quantum computing settings.
Generating samples from the output distribution of a quantum circuit is a ubiquitous task used as a building block of many quantum algorithms. Here we show how to accomplish this task on a noisy quantum processor lacking full-blown error correction for a special class of quantum circuits dominated by Clifford gates. Our approach is based on coherent Pauli checks (CPCs) that detect errors in a Clifford circuit by verifying commutation rules between random Pauli-type check operators and the considered circuit. Our main contributions are as follows. First, we derive a simple formula for the probability that a Clifford circuit protected by CPCs contains a logical error. In the limit of a large number of checks, the logical error probability is shown to approach the value $\ensuremath{\approx}7\ensuremath{\epsilon}n/5$, where nnn is the number of qubits and $\ensuremath{\epsilon}$ is the depolarizing error rate. Our formula agrees nearly perfectly with the numerical simulation results. Second, we show that CPCs are well suited for quantum processors with a limited qubit connectivity. For example, the difference between all-to-all and linear qubit connectivity is only a $3\ifmmode\times\else\texttimes\fi{}$ increase in the number of cnot gates required to implement CPCs. Third, we describe simplified one-sided CPCs, which are well suited for mitigating measurement errors in the single-shot settings. Finally, we report an experimental demonstration of CPCs with up to 10 logical qubits and more than 100 logical cnot gates. Our experimental results show that CPCs provide a marked improvement in the logical error probability for the considered task of sampling the output distribution of quantum circuits.