Quantum computation promises asymptotic speedups over classical algorithms, but realizing these advantages requires overcoming the noisiness of quantum hardware. Although fault-tolerant error correction can allow for reliable quantum computation even using unreliable components, the resource overheads required can substantially erode the asymptotic performance gains. This dissertation focuses on constructing and optimizing fault-tolerant procedures with lower overhead than previous methods were capable of. We present new frameworks for fault-tolerant syndrome extraction using flag gadgets with exponentially reduced ancilla requirements, explicit measurement schedules that achieve asymptotically fewer measurements than stabilizer generators, and a general method for making arbitrary Clifford circuits fault tolerant. In addition, we optimize surface code measurement schedules in the presence of constraints imposed by fabrication defects to reduce logical error rate. Together, these results advance low-overhead fault tolerance and improve performance in resource-constrained and near-term quantum computing settings.
Quantum computation promises asymptotic speedups over classical algorithms, but realizing these advantages requires overcoming the noisiness of quantum hardware. Although fault-tolerant error correction can allow for reliable quantum computation even using unreliable components, the resource overheads required can substantially erode the asymptotic performance gains. This dissertation focuses on constructing and optimizing fault-tolerant procedures with lower overhead than previous methods were capable of. We present new frameworks for fault-tolerant syndrome extraction using flag gadgets with exponentially reduced ancilla requirements, explicit measurement schedules that achieve asymptotically fewer measurements than stabilizer generators, and a general method for making arbitrary Clifford circuits fault tolerant. In addition, we optimize surface code measurement schedules in the presence of constraints imposed by fabrication defects to reduce logical error rate. Together, these results advance low-overhead fault tolerance and improve performance in resource-constrained and near-term quantum computing settings.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Quantum error detection (QED) offers a promising pathway to fault tolerance in near-term quantum devices by balancing error suppression with minimal resource overhead. However, its practical utility hinges on optimizing design parameters-such as syndrome measurement frequency-to avoid diminishing returns from detection overhead. In this work, we present a comprehensive framework for fault-tolerant compilation and simulation of quantum algorithms using [[n, n-2, 2]] codes, which enable low-qubit-overhead error detection and a simple nearly fault-tolerant universal set of operations. We demonstrate and analyze our pipeline with a purely statistical interpretation and through the implementation of Grover's search algorithm. Our results are used to answer the question is quantum error detection a worthwhile avenue for early-term fault tolerance, and if so how can we get the most out of it? Simulations under the circuit-level noise model reveal that finding optimal syndrome schedules improves algorithm success probabilities by an average of 6.7x but eventual statistical limits from post-selection in noisy/resource-limited regimes constrain scalability. Furthermore, we propose a simple data-driven approach to predict fault tolerant compilation parameters, such as optimal syndrome schedules, and expected fault tolerant performance gains based on circuit and noise features. These results provide actionable guidelines for implementing QED in early-term quantum experiments and underscore its role as a pragmatic, constant-overhead error mitigation layer for shallow algorithms. To aid in further research, we release all simulation data computed for this work and provide an experimental QED compiler at https://codeqraft.xyz/qed.
Fault-tolerant error-correction (FTEC) circuit is the foundation for achieving reliable quantum computation and remote communication. However, designing a fault-tolerant error correction scheme with a solid error-correction ability and low overhead remains a significant challenge. In this paper, a low-overhead fault-tolerant error correction scheme is proposed for quantum communication systems. Firstly, syndrome ancillas are prepared into Bell states to detect errors caused by channel noise. We propose a detection approach that reduces the propagation path of quantum gate fault and reduces the circuit depth by splitting the stabilizer generator into X-type and Z-type. Additionally, a syndrome extraction circuit is equipped with two flag qubits to detect quantum gate faults, which may also introduce errors into the code block during the error detection process. Finally, analytical results are provided to demonstrate the fault-tolerant performance of the proposed FTEC scheme with the lower overhead of the ancillary qubits and circuit depth.
We reduce the extra qubits needed for two fault-tolerant quantum computing protocols: error correction, specifically syndrome bit measurement, and cat state preparation. For distance-three fault-tolerant syndrome extraction, we show an exponential reduction in qubit overhead over the previous best protocol. For a weight- w stabilizer, we demonstrate that stabilizer measurement tolerating one fault needs at most ⌈log2w⌉+1 ancilla qubits. If qubits reset quickly, four ancillas suffice. We also study the preparation of entangled cat states, and prove that the overhead for distance-three fault tolerance is logarithmic in the cat state size. These results apply both to near-term experiments with a few qubits, and to the general study of the asymptotic resource requirements of syndrome measurement and state preparation.With a flag qubits, previous methods use O(a) flag patterns to identify faults. In order to use the same flag qubits more efficiently, we show how to use nearly all 2a possible flag patterns, by constructing maximal-length paths through the a -dimensional hypercube.
Quantum Arithmetic Logic Units (ALUs) serve as critical components in quantum processors, enabling both arithmetic and logical operations on qubits. However, the fragile nature of quantum systems makes them susceptible to errors and decoherence, necessitating fault-tolerant designs. In this work, we propose a fault-tolerant quantum ALU architecture constructed using the Clifford+ T gate set, which is widely recognized for its compatibility with error-correcting codes. The proposed design minimizes quantum resource overhead while maintaining computational accuracy under fault-prone conditions. Notably, the architecture requires zero ancilla and generates a single garbage output, optimizing the qubit space. Performance evaluations demonstrate significant improvements, achieving a 31.8% reduction in T-count and a 33.3% reduction in T-depth compared to existing designs. These enhancements contribute to more efficient and reliable quantum computation, paving the way for scalable quantum processor development.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.