Characterizing Physical and Logical Errors in a Transversal CNOT Gate via Cycle Error Reconstruction
Nicholas Fazio, Robert Freund, Debankan Sannamoth, Alex Steiner, Christian D. Marciniak, Manuel Rispler, Robin Harper, Thomas Monz, Joseph Emerson, Stephen D. Bartlett
The development of prototype quantum information processors has progressed to a stage where small instances of logical qubit systems perform better than the best of their physical constituents. Advancing toward fault-tolerant quantum computing will require an understanding of the underlying error mechanisms in logical primitives as they relate to the performance of quantum error correction. In this work we demonstrate the novel capability to characterize the physical error properties relevant to fault-tolerant operations via cycle error reconstruction. We illustrate this diagnostic capability for a transversal controlled- () gate, a prototypical component of quantum logical operations, in a 16-qubit register of a trapped-ion quantum computer. Our error characterization technique offers three key capabilities: (i) identifying context-dependent physical layer errors, enabling their mitigation, (ii) contextualizing component gates in the environment of logical operators, validating the performance differences in terms of characterized component-level physics, and (iii) providing a scalable method for predicting quantum error correction performance using pertinent error terms, differentiating correctable versus uncorrectable physical layer errors. The methods with which our results are obtained have scalable resource requirements that can be extended with moderate overhead to capture overall logical performance in increasingly large and complex systems.
The development of prototype quantum information processors has progressed to a stage where small instances of logical qubit systems perform better than the best of their physical constituents. Advancing toward fault-tolerant quantum computing will require an understanding of the underlying error mechanisms in logical primitives as they relate to the performance of quantum error correction. In this work we demonstrate the novel capability to characterize the physical error properties relevant to fault-tolerant operations via cycle error reconstruction. We illustrate this diagnostic capability for a transversal controlled- () gate, a prototypical component of quantum logical operations, in a 16-qubit register of a trapped-ion quantum computer. Our error characterization technique offers three key capabilities: (i) identifying context-dependent physical layer errors, enabling their mitigation, (ii) contextualizing component gates in the environment of logical operators, validating the performance differences in terms of characterized component-level physics, and (iii) providing a scalable method for predicting quantum error correction performance using pertinent error terms, differentiating correctable versus uncorrectable physical layer errors. The methods with which our results are obtained have scalable resource requirements that can be extended with moderate overhead to capture overall logical performance in increasingly large and complex systems.
The development of prototype quantum information processors has progressed to a stage where small instances of logical qubit systems perform better than the best of their physical constituents.Advancing toward fault-tolerant quantum computing will require an understanding of the underlying error mechanisms in logical primitives as they relate to the performance of quantum error correction.In this work we demonstrate the novel capability to characterize the physical error properties relevant to fault-tolerant operations via cycle error reconstruction.We illustrate this diagnostic capability for a transversal controlled-NOT (CNOT) gate, a prototypical component of quantum logical operations, in a 16-qubit register of a trapped-ion quantum computer.Our error characterization technique offers three key capabilities: (i) identifying context-dependent physical layer errors, enabling their mitigation, (ii) contextualizing component gates in the environment of logical operators, validating the performance differences in terms of characterized component-level physics, and (iii) providing a scalable method for predicting quantum error correction performance using pertinent error terms, differentiating correctable versus uncorrectable physical layer errors.The methods with which our results are obtained have scalable resource requirements that can be extended with moderate overhead to capture overall logical performance in increasingly large and complex systems.
The full potential of quantum computers will be attainable when large devices can employ quantum error correction and attain fault-tolerance. Great strides have been made, with experimental demonstrations of pivotal components for quantum error correction on a variety of platforms, substantiating that the foundations for fault-tolerant logic are realisable. This thesis explores the kinds of noise we expect to find at the logical level while employing schemes for fault-tolerance in this emerging period and how we may optimise such schemes. We study how a noise characteristic called bias is transformed in the implementation of a fault-tolerant gadget for the T-gate. We show that noise bias is amplified at the logical level due to error correction, which is furthermore affected by the noise-transforming properties of the injection gadget, which separately induces logical phase bias. We experimentally characterise the noise on a trapped-ion quantum computer. We target a logical CNOT with this method such that we are able to: understand and mitigate control layer imperfections, account for the distinction in noise characteristics between individual CNOT and transversal CNOTs, and make predictions on logical level performance if these transversal CNOTs are used as a logical CNOT for the Steane code. This is achieved by leveraging information about correlated noise across the device from the physical characterisation of gates, demonstrating that such diagnostic information can be learned scalably. Finally, noting the transversal gate capabilities of recent architectures, we optimise fault-tolerant circuits for preparing magic states in that setting. We describe an algorithm that recompiles and synthesises such circuits for minimal T-depth and low CNOT depth, while maintaining the total qubit count. We apply this algorithm to fault-tolerant circuits for |CCZ>, |CS> and |T> and show how we can reduce overheads for preparing magic states.
A scalable and programmable quantum computer holds the potential to solve computationally intensive tasks that classical computers cannot accomplish within a reasonable time frame, achieving quantum advantage. However, the vulnerability of the current generation of quantum processors to errors poses a significant challenge towards executing complex and deep quantum circuits required for practical problems. Quantum error-correction codes such as stabilizer codes offer a promising path forward for fault-tolerant quantum computing; however, their realization on quantum hardware is an on-going area of research. In particular, fault-tolerant quantum processing must employ logical gates on logical qubits with error suppression with realistically large size codes. This work has implemented a transversal controlled-not (cnot) gate between two logical qubits constructed using the repetition code with flag qubits, and demonstrated error suppression with increasing code size under multiple rounds of error detection and correction. Our results conducted on IBM quantum devices through cloud access show that despite the potential for error propagation among logical qubits during the transversal cnot gate operation, scaling the code distance as we increase the number of physical qubits from 21 to 39 and 57 can suppress errors, which persists over ten rounds of error detection and correction. Our work establishes the feasibility of employing logical cnot gates alongside error detection on a superconductor-based processor using current generation quantum hardware.
Scaling up quantum algorithms to tackle high-impact problems in science and industry requires quantum error correction and fault tolerance. While progress has been made in experimentally realizing error-corrected primitives, the end-to-end execution of logical quantum algorithms using only fault-tolerant (FT) components has remained out of reach. We demonstrate the FT and error-corrected execution of two quantum algorithms, the Quantum Approximate Optimization Algorithm (QAOA) and the Harrow-Hassidim-Lloyd (HHL) algorithm applied to the Poisson equation, on Quantinuum H2 and Helios trapped-ion quantum processors using the [[7,1,3]] Steane code. For QAOA circuits on 5 and 6 logical qubits, we show performance improvements from increasing the number of QAOA layers and the number of T gates used to approximate logical rotations, despite increased physical circuit complexity. We further show that QAOA circuits with up to 8 logical qubits and 9 logical T gates perform similarly to unencoded circuits. For the largest QAOA circuits we run, with 12 logical (97 physical) qubits and 2132 physical two-qubit gates, we still observe better-than-random performance. Finally, we show that adding active QEC cycles and increasing the repeat-until-success limit of state preparation subroutines can improve the performance of a quantum algorithm, thereby demonstrating critical capabilities of scalable FT quantum computation. Our results are enabled by an FT logical T gate implementation with an infidelity of ∼2.6(4)×10−3 and dynamic circuits with measurement-dependent feedback. Our work demonstrates near-break-even performance of complex, error-corrected algorithmic quantum circuits using only FT components.
The promise of quantum computers hinges on the ability to scale to large system sizes, e.g., to run quantum computations consisting of more than 100 million operations fault-tolerantly. This in turn requires suppressing errors to levels inversely proportional to the size of the computation. As a step towards this ambitious goal, we present experiments on a trapped-ion QCCD processor where, through the use of fault-tolerant encoding and error correction, we are able to suppress logical error rates to levels below the physical error rates. In particular, we entangled logical qubits encoded in the [[7,1,3]] code with error rates 9.8 times to 500 times lower than at the physical level, and entangled logical qubits encoded in a [[12,2,4]] code based on Knill's C4/C6 scheme with error rates 4.7 times to 800 times lower than at the physical level, depending on the judicious use of post-selection. Moreover, we demonstrate repeated error correction with the [[12,2,4]] code, with logical error rates below physical circuit baselines corresponding to repeated CNOTs, and show evidence that the error rate per error correction cycle, which consists of over 100 physical CNOTs, approaches the error rate of two physical CNOTs. These results signify a transition from noisy intermediate scale quantum computing to reliable quantum computing, and demonstrate advanced capabilities toward large-scale fault-tolerant quantum computing.
Logical qubits can be protected from decoherence by performing QEC cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory that operates for in principle arbitrary long times. All circuit components must be assumed as noisy unless specific assumptions about the form of the noise are made. Modern QEC schemes are challenging to implement experimentally in physical architectures where in-sequence measurements and feed-forward of classical information cannot be reliably executed fast enough or even at all. Here we provide a novel scheme to perform QEC cycles without the need of measuring qubits that is fully fault-tolerant with respect to all components used in the circuit. Our scheme can be used for any low-distance CSS code since its only requirement towards the underlying code is a transversal CNOT gate. Similarly to Steane-type EC, we coherently copy errors to a logical auxiliary qubit but then apply a coherent feedback operation from the auxiliary system to the logical data qubit. The logical auxiliary qubit is prepared fault-tolerantly without measurements, too. We benchmark logical failure rates of the scheme in comparison to a flag-qubit based EC cycle. We map out a parameter region where our scheme is feasible and estimate physical error rates necessary to achieve the break-even point of beneficial QEC with our scheme. We outline how our scheme could be implemented in ion traps and with neutral atoms in a tweezer array. For recently demonstrated capabilities of atom shuttling and native multi-atom Rydberg gates, we achieve moderate circuit depths and beneficial performance of our scheme while not breaking fault tolerance. These results thereby enable practical fault-tolerant QEC in hardware architectures that do not support mid-circuit measurements.