The full potential of quantum computers will be attainable when large devices can employ quantum error correction and attain fault-tolerance. Great strides have been made, with experimental demonstrations of pivotal components for quantum error correction on a variety of platforms, substantiating that the foundations for fault-tolerant logic are realisable. This thesis explores the kinds of noise we expect to find at the logical level while employing schemes for fault-tolerance in this emerging period and how we may optimise such schemes. We study how a noise characteristic called bias is transformed in the implementation of a fault-tolerant gadget for the T-gate. We show that noise bias is amplified at the logical level due to error correction, which is furthermore affected by the noise-transforming properties of the injection gadget, which separately induces logical phase bias. We experimentally characterise the noise on a trapped-ion quantum computer. We target a logical CNOT with this method such that we are able to: understand and mitigate control layer imperfections, account for the distinction in noise characteristics between individual CNOT and transversal CNOTs, and make predictions on logical level performance if these transversal CNOTs are used as a logical CNOT for the Steane code. This is achieved by leveraging information about correlated noise across the device from the physical characterisation of gates, demonstrating that such diagnostic information can be learned scalably. Finally, noting the transversal gate capabilities of recent architectures, we optimise fault-tolerant circuits for preparing magic states in that setting. We describe an algorithm that recompiles and synthesises such circuits for minimal T-depth and low CNOT depth, while maintaining the total qubit count. We apply this algorithm to fault-tolerant circuits for |CCZ>, |CS> and |T> and show how we can reduce overheads for preparing magic states.
The full potential of quantum computers will be attainable when large devices can employ quantum error correction and attain fault-tolerance. Great strides have been made, with experimental demonstrations of pivotal components for quantum error correction on a variety of platforms, substantiating that the foundations for fault-tolerant logic are realisable. This thesis explores the kinds of noise we expect to find at the logical level while employing schemes for fault-tolerance in this emerging period and how we may optimise such schemes. We study how a noise characteristic called bias is transformed in the implementation of a fault-tolerant gadget for the T-gate. We show that noise bias is amplified at the logical level due to error correction, which is furthermore affected by the noise-transforming properties of the injection gadget, which separately induces logical phase bias. We experimentally characterise the noise on a trapped-ion quantum computer. We target a logical CNOT with this method such that we are able to: understand and mitigate control layer imperfections, account for the distinction in noise characteristics between individual CNOT and transversal CNOTs, and make predictions on logical level performance if these transversal CNOTs are used as a logical CNOT for the Steane code. This is achieved by leveraging information about correlated noise across the device from the physical characterisation of gates, demonstrating that such diagnostic information can be learned scalably. Finally, noting the transversal gate capabilities of recent architectures, we optimise fault-tolerant circuits for preparing magic states in that setting. We describe an algorithm that recompiles and synthesises such circuits for minimal T-depth and low CNOT depth, while maintaining the total qubit count. We apply this algorithm to fault-tolerant circuits for |CCZ>, |CS> and |T> and show how we can reduce overheads for preparing magic states.
Fault-tolerant architectures aim to reduce the noise of a quantum computation. Despite such architectures being well studied a detailed understanding of how noise is transformed in a fault-tolerant primitive such as magic state injection is currently lacking. We use numerical simulations of logical process tomography on a fault-tolerant gadget that implements a logical T=Z(π/4) gate using magic state injection, to understand how noise characteristics at the physical level are transformed into noise characteristics at the logical level. We show how, in this gadget, a significant phase ( Z ) bias can arise in the logical noise, even with unbiased noise at the physical level. While the magic state injection gadget intrinsically induces biased noise, with extant phase bias being further amplified at the logical level, we identify noisy error correction circuits as a key limiting factor in the circuits studied on the magnitude of this logical noise bias. Our approach provides a framework for assessing the detailed noise characteristics, as well as the overall performance, of fault-tolerant logical primitives.
The development of prototype quantum information processors has progressed to a stage where small instances of logical qubit systems perform better than the best of their physical constituents. Advancing toward fault-tolerant quantum computing will require an understanding of the underlying error mechanisms in logical primitives as they relate to the performance of quantum error correction. In this work we demonstrate the novel capability to characterize the physical error properties relevant to fault-tolerant operations via cycle error reconstruction. We illustrate this diagnostic capability for a transversal controlled- () gate, a prototypical component of quantum logical operations, in a 16-qubit register of a trapped-ion quantum computer. Our error characterization technique offers three key capabilities: (i) identifying context-dependent physical layer errors, enabling their mitigation, (ii) contextualizing component gates in the environment of logical operators, validating the performance differences in terms of characterized component-level physics, and (iii) providing a scalable method for predicting quantum error correction performance using pertinent error terms, differentiating correctable versus uncorrectable physical layer errors. The methods with which our results are obtained have scalable resource requirements that can be extended with moderate overhead to capture overall logical performance in increasingly large and complex systems.
The development of prototype quantum information processors has progressed to a stage where small instances of logical qubit systems perform better than the best of their physical constituents.Advancing toward fault-tolerant quantum computing will require an understanding of the underlying error mechanisms in logical primitives as they relate to the performance of quantum error correction.In this work we demonstrate the novel capability to characterize the physical error properties relevant to fault-tolerant operations via cycle error reconstruction.We illustrate this diagnostic capability for a transversal controlled-NOT (CNOT) gate, a prototypical component of quantum logical operations, in a 16-qubit register of a trapped-ion quantum computer.Our error characterization technique offers three key capabilities: (i) identifying context-dependent physical layer errors, enabling their mitigation, (ii) contextualizing component gates in the environment of logical operators, validating the performance differences in terms of characterized component-level physics, and (iii) providing a scalable method for predicting quantum error correction performance using pertinent error terms, differentiating correctable versus uncorrectable physical layer errors.The methods with which our results are obtained have scalable resource requirements that can be extended with moderate overhead to capture overall logical performance in increasingly large and complex systems.
Qubits with strongly biased noise, in which phase-flip errors are orders of magnitude more frequent than bit-flips, arise both naturally, as in electron and nuclear spins, and by engineering, as in stabilized cat qubits. This noise structure holds the promise of reducing the daunting hardware overhead of fault-tolerant quantum computing, but exploiting it requires physical operations that do not convert frequent phase-flips into rare bit-flips. In this review, we analyze the most prominent fault-tolerant protocols for biased-noise qubits, organized according to the available set of such bias-preserving operations. When this set is restricted to the CZ gate together with preparation and measurement in the X basis, we show that the complexity of the required syndrome extraction gadgets essentially cancels the benefit of the noise bias: at experimentally relevant error rates, one may as well ignore the bias and rely on standard error correction designed for depolarizing noise. The situation changes drastically when a bias-preserving CX gate is available: the hierarchy of errors can then be reflected in the structure of the code, with frequent phase-flips corrected by a dedicated high-threshold code and rare bit-flips by concatenation with a high-rate code. The same hierarchy also enables hardware-efficient preparation of magic states. Finally, as a bias-preserving CX is forbidden in naturally biased platforms and challenging in engineered ones, we present a measurement-based architecture in which a high-fidelity quantum non-demolition readout of multi-qubit Pauli Z operators takes its place, extending these overhead reductions to a much broader range of physical platforms.
Fault-tolerant quantum error correction provides a strategy to protect information processed by a quantum computer against noise which would otherwise corrupt the data. A fault-tolerant universal quantum computer must implement a universal gate set on the logical level in order to perform arbitrary calculations to in principle unlimited precision. In this paper we characterize the recent demonstration of a fault-tolerant universal gate set in a trapped-ion quantum computer [Postler et al., Nature (London) 605, 7911 (2022)] and identify aspects to improve the design of experimental setups to reach an advantage of logical over physical qubit operation. We show that various criteria to assess the break-even point for fault-tolerant quantum operations are within reach for the ion trap quantum computing architecture under consideration. Furthermore, we analyze the influence of crosstalk in entangling gates for logical state preparation circuits. These circuits can be designed to respect fault tolerance for specific microscopic noise models. We find that an experimentally informed depolarizing noise model captures the essential noise dynamics of the fault-tolerant experiment that we consider, and crosstalk is negligible in the currently accessible regime of physical error rates. For deterministic Pauli state preparation, we provide a fault-tolerant unitary logical qubit initialization circuit, which can be realized without in-sequence measurement and feed-forward of classical information. Additionally, we show that nondeterministic state preparation schemes, i.e., repeat until success, for logical Pauli and magic states perform with higher logical fidelity over their deterministic counterparts for the current and anticipated future regime of physical error rates. Our results offer guidance on improvements of physical qubit operations and validate the experimentally informed noise model as a tool to predict logical failure rates in quantum computing architectures based on trapped ions.
Noise is the fundamental challenge to quantum computation. Large-scale quantum computers will overcome this challenge with fault-tolerant architectures that leverage quantum error correction. This thesis introduces and investigates a scalable noise characterisation protocol suited to this key context. First, we introduce this protocol by building upon averaged circuit eigenvalue sampling (ACES), a framework for noise characterisation experiments that simultaneously estimates the Pauli error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise characterisation procedure. Then we demonstrate in circuit-level numerical simulation that this protocol is practically capable of calibrating a fast correlated matching decoder, enabling noise-aware decoding. We find that noise-aware decoding increases the error suppression factor of the code, leading to reductions in the logical error rate that increase exponentially with the code distance. Finally, we present several results obtained from experimentally implementing this protocol. We use the noise characterisation results to design an improved syndrome extraction circuit for a heavy hexagon memory that is adapted to the noise characteristics of the quantum device. The model error of our noise characterisation results suggests that the circuit-level Pauli noise model estimated by ACES can describe the essential features of quantum noise. We also operate a heavy hexagon memory and use noise estimates to predict performance and inform decoding. These results demonstrate that Pauli noise estimates can calibrate decoders to enable noise-aware decoding and inform the co-design of quantum error correcting codes, decoders, fault-tolerant circuits, and quantum devices.