A scalable and programmable quantum computer holds the potential to solve computationally intensive tasks that classical computers cannot accomplish within a reasonable time frame, achieving quantum advantage. However, the vulnerability of the current generation of quantum processors to errors poses a significant challenge towards executing complex and deep quantum circuits required for practical problems. Quantum error-correction codes such as stabilizer codes offer a promising path forward for fault-tolerant quantum computing; however, their realization on quantum hardware is an on-going area of research. In particular, fault-tolerant quantum processing must employ logical gates on logical qubits with error suppression with realistically large size codes. This work has implemented a transversal controlled-not (cnot) gate between two logical qubits constructed using the repetition code with flag qubits, and demonstrated error suppression with increasing code size under multiple rounds of error detection and correction. Our results conducted on IBM quantum devices through cloud access show that despite the potential for error propagation among logical qubits during the transversal cnot gate operation, scaling the code distance as we increase the number of physical qubits from 21 to 39 and 57 can suppress errors, which persists over ten rounds of error detection and correction. Our work establishes the feasibility of employing logical cnot gates alongside error detection on a superconductor-based processor using current generation quantum hardware.
A scalable and programmable quantum computer holds the potential to solve computationally intensive tasks that classical computers cannot accomplish within a reasonable time frame, achieving quantum advantage. However, the vulnerability of the current generation of quantum processors to errors poses a significant challenge towards executing complex and deep quantum circuits required for practical problems. Quantum error-correction codes such as stabilizer codes offer a promising path forward for fault-tolerant quantum computing; however, their realization on quantum hardware is an on-going area of research. In particular, fault-tolerant quantum processing must employ logical gates on logical qubits with error suppression with realistically large size codes. This work has implemented a transversal controlled-not (cnot) gate between two logical qubits constructed using the repetition code with flag qubits, and demonstrated error suppression with increasing code size under multiple rounds of error detection and correction. Our results conducted on IBM quantum devices through cloud access show that despite the potential for error propagation among logical qubits during the transversal cnot gate operation, scaling the code distance as we increase the number of physical qubits from 21 to 39 and 57 can suppress errors, which persists over ten rounds of error detection and correction. Our work establishes the feasibility of employing logical cnot gates alongside error detection on a superconductor-based processor using current generation quantum hardware.
Code switching is an established technique that facilitates a universal set of FT quantum gate operations by combining two QEC codes with complementary sets of gates, which each by themselves are easy to implement fault-tolerantly. In this work, we present a code switching scheme that respects the constraints of FT circuit design by only making use of transversal gates. These gates are intrinsically FT without additional qubit overhead. We analyze application of the scheme to low-distance color codes, which are suitable for operation in existing quantum processors, for instance based on trapped ions or neutral atoms. We briefly discuss connectivity constraints that arise for architectures based on superconducting qubits. Numerical simulations of circuit-level noise indicate that a logical T -gate, facilitated by our scheme, could outperform both flag-FT magic state injection protocols and a physical T -gate at low physical error rates. Transversal code switching naturally scales to code pairs of arbitrary code distance. We observe improved performance of a distance-5 protocol compared to both the distance-3 implementation and the physical gate for realistically attainable physical entangling gate error rates. We discuss how the scheme can be implemented with a large degree of parallelization, provided that logical auxiliary qubits can be prepared reliably enough. Our logical T -gate circumvents potentially costly magic state factories. The requirements to perform QEC and to achieve an FT universal gate set are then essentially the same: Prepare logical auxiliary qubits offline, execute transversal gates and perform fast-enough measurements. Transversal code switching thus serves to enable more practical hardware realizations of FT universal quantum computation. The scheme alleviates resource requirements for experimental demonstrations of quantum algorithms run on logical qubits.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
We compare two different implementations of fault-tolerant entangling gates on logical qubits. In one instance, a twelve-qubit trapped-ion quantum computer is used to implement a non-transversal logical CNOT gate between two five qubit codes. The operation is evaluated with varying degrees of fault tolerance, which are provided by including quantum error correction circuit primitives known as flagging and pieceable fault tolerance. In the second instance, a twenty-qubit trapped-ion quantum computer is used to implement a transversal logical CNOT gate on two [[7,1,3]] color codes. The two codes were implemented on different but similar devices, and in both instances, all of the quantum error correction primitives, including the determination of corrections via decoding, are implemented during runtime using a classical compute environment that is tightly integrated with the quantum processor. For different combinations of the primitives, logical state fidelity measurements are made after applying the gate to different input states, providing bounds on the process fidelity. We find the highest fidelity operations with the color code, with the fault-tolerant SPAM operation achieving fidelities of 0.99939(15) and 0.99959(13) when preparing eigenstates of the logical X and Z operators, which is higher than the average physical qubit SPAM fidelities of 0.9968(2) and 0.9970(1) for the physical X and Z bases, respectively. When combined with a logical transversal CNOT gate, we find the color code to perform the sequence--state preparation, CNOT, measure out--with an average fidelity bounded by [0.9957,0.9963]. The logical fidelity bounds are higher than the analogous physical-level fidelity bounds, which we find to be [0.9850,0.9903], reflecting multiple physical noise sources such as SPAM errors for two qubits, several single-qubit gates, a two-qubit gate and some amount of memory error.
Realizing the potential of quantum computing will require achieving sufficiently low logical error rates. Many applications call for error rates in the 10−15 regime, but state-of-the-art quantum platforms typically have physical error rates near 10−3. Quantum error correction (QEC) promises to bridge this divide by distributing quantum logical information across many physical qubits so that errors can be detected and corrected. Logical errors are then exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold. QEC also requires that the errors are local and that performance is maintained over many rounds of error correction, two major outstanding experimental challenges. Here, we implement 1D repetition codes embedded in a 2D grid of superconducting qubits which demonstrate exponential suppression of bit or phase-flip errors, reducing logical error per round by more than 100× when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analyzing error correlations with high precision, and characterize the locality of errors in a device performing QEC for the first time. Finally, we perform error detection using a small 2D surface code logical qubit on the same device, and show that the results from both 1D and 2D codes agree with numerical simulations using a simple depolarizing error model. These findings demonstrate that superconducting qubits are on a viable path towards fault tolerant quantum computing.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
We present a set of efficiently implementable logical multi-qubit gates in concatenated quantum error correction codes using parity qubits. In particular, we show how fault-tolerant high-weight rotation gates of arbitrary angle can be implemented on single physical qubits of a classical stabilizer code, or on localized regions of full quantum error correction codes. Similarly, we show how transversal CNOT gates can implement logical parity-controlled-NOT operations between arbitrarily many logical qubits. Both operation types can be implemented and in many cases parallelized without the use of lattice surgery or the need for complicated routing operations.