Mid-circuit measurements used in quantum error correction are essential in the architecture of a fault-tolerant quantum computer, as they read out syndrome data and drive logic gates. Here, we use a heavy-hex code prepared on a superconducting qubit array to investigate how different noise sources impact error-corrected logic. First, we identify that idling errors occurring during readout periods are highly detrimental to a quantum memory. We demonstrate significant improvements to the memory by designing and implementing a low-depth syndrome extraction circuit. Second, we perform a stability experiment to investigate the type of failures that can occur during logic gates due to readout assignment errors. We find that the error rate of the stability experiment improves with additional stabilizer readout cycles, revealing a trade-off as additional stability comes at the expense of time over which the memory can decay. We corroborate our results using holistic device benchmarking and by comparison to numerical simulations. Finally, by varying different parameters in our simulations we identify the key noise sources that impact the fidelity of fault-tolerant logic gates, with measurement noise playing a dominant role in logical gate performance. With rapid progress in quantum error correction, clear performance benchmarks are needed to assess readiness for fault tolerant operation. Here the authors report benchmarking and noise characterization in a superconducting quantum processor, identifying key factors that impact error-corrected logic.
Mid-circuit measurements used in quantum error correction are essential in the architecture of a fault-tolerant quantum computer, as they read out syndrome data and drive logic gates. Here, we use a heavy-hex code prepared on a superconducting qubit array to investigate how different noise sources impact error-corrected logic. First, we identify that idling errors occurring during readout periods are highly detrimental to a quantum memory. We demonstrate significant improvements to the memory by designing and implementing a low-depth syndrome extraction circuit. Second, we perform a stability experiment to investigate the type of failures that can occur during logic gates due to readout assignment errors. We find that the error rate of the stability experiment improves with additional stabilizer readout cycles, revealing a trade-off as additional stability comes at the expense of time over which the memory can decay. We corroborate our results using holistic device benchmarking and by comparison to numerical simulations. Finally, by varying different parameters in our simulations we identify the key noise sources that impact the fidelity of fault-tolerant logic gates, with measurement noise playing a dominant role in logical gate performance. With rapid progress in quantum error correction, clear performance benchmarks are needed to assess readiness for fault tolerant operation. Here the authors report benchmarking and noise characterization in a superconducting quantum processor, identifying key factors that impact error-corrected logic.
Large quantum computations require high-fidelity error-corrected memory and fault-tolerant logical operations. To achieve these with superconducting circuits, quantum processors will need many components operating with low error rates. In practice, fabrication of monolithic superconducting devices produces unavoidable heterogeneity in component performance, which the quantum computer must accommodate. We implement strategies to operate a large dynamic compass code on an array of 156 superconducting qubits arranged on a heavy-hexagonal lattice, making use of the entire monolithic quantum processor and redesigning our measurement schedule to exclude underperforming components. We demonstrate improvements of up to 35% in logical error probabilities for a memory experiment by using a noise-informed decoder combined with strategies to exclude the worst-performing qubits and couplers, along with post-selecting on shots with a low probability of leakage errors. In addition to these memory results, we also observe performance gains of up to 56% when these strategies are applied to measurement-based logic, demonstrated by stability experiments. We furthermore demonstrate high-fidelity fault-tolerant logic through lattice surgery. Through pre-selection filtering techniques, we can obtain Bell fidelities above 77%, and further logical gap post-selection using exclusive decoding increases these fidelities to above 97%. Our experiments demonstrate that high performance can be maintained in key elements of fault-tolerant quantum memory and logic when working on monolithic superconducting quantum processors with underperforming components, by using a suite of noise-informed quantum error correction strategies.
With quantum devices rapidly approaching qualities and scales needed for fault tolerance, the validity of simplified error models underpinning the study of quantum error correction needs to be experimentally evaluated. In this work, we have assessed the performance of IBM superconducting quantum computer devices implementing heavy-hexagon code syndrome measurements with circuit sizes up to 23 qubits, against the error assumptions underpinning code threshold calculations. Circuit operator change rate statistics in the presence of depolarizing and biased noise were modeled using analytic functions of error model parameters. Data from 16 repeated syndrome measurement cycles were found to be inconsistent with a uniform depolarizing noise model, with slightly improved fits found with biased and inhomogeneous noise models. Spatial-temporal correlations investigated via Z stabilizer measurements revealed significant temporal correlation in detection events. These results highlight the nontrivial structure that may be present in the noise of quantum error correction circuits, revealed by operator measurement statistics, and support the development of noise-tailored codes and decoders to adapt. Published by the American Physical Society 2024
Quantum error correcting code can diagnose potential errors and correct them based on measured outcomes by leveraging syndrome measurement. However, mid-circuit measurement has been technically challenging for early fault-tolerant quantum computers and the readout-induced noise acts as a main contributor to the logical infidelity. We present a different method for syndrome extraction, namely , that requires only a single-shot measurement on a single ancilla, while the canonical syndrome measurement requires multiple measurements to extract the eigenvalue for each stabilizer generator. As such, we can detect the error in the logical state with minimized readout-induced noise. By adopting our method as a precheck routine for quantum error correcting cycles, we can significantly reduce the readout overhead, the idling time, and the logical error rate during syndrome measurement. We numerically analyze the performance of our protocol using Iceberg code and Steane code under realistic noise parameters based on superconducting hardware and demonstrate the advantage of our protocol in the near-term scenario. As mid-circuit measurements are still error-prone for near-term quantum hardware, our method could boost the applications of early fault-tolerant quantum computing. Published by the American Physical Society 2024
Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.
Quantum error correction protects fragile quantum information by encoding it into a larger quantum system. These extra degrees of freedom enable the detection and correction of errors, but also increase the operational complexity of the encoded logical qubit. Fault-tolerant circuits contain the spread of errors while operating the logical qubit, and are essential for realizing error suppression in practice. While fault-tolerant design works in principle, it has not previously been demonstrated in an error-corrected physical system with native noise characteristics. In this work, we experimentally demonstrate fault-tolerant preparation, measurement, rotation, and stabilizer measurement of a Bacon-Shor logical qubit using 13 trapped ion qubits. When we compare these fault-tolerant protocols to non-fault tolerant protocols, we see significant reductions in the error rates of the logical primitives in the presence of noise. The result of fault-tolerant design is an average state preparation and measurement error of 0.6% and a Clifford gate error of 0.3% after error correction. Additionally, we prepare magic states with fidelities exceeding the distillation threshold, demonstrating all of the key single-qubit ingredients required for universal fault-tolerant operation. These results demonstrate that fault-tolerant circuits enable highly accurate logical primitives in current quantum systems. With improved two-qubit gates and the use of intermediate measurements, a stabilized logical qubit can be achieved.
Noise is the fundamental challenge to quantum computation. Large-scale quantum computers will overcome this challenge with fault-tolerant architectures that leverage quantum error correction. This thesis introduces and investigates a scalable noise characterisation protocol suited to this key context. First, we introduce this protocol by building upon averaged circuit eigenvalue sampling (ACES), a framework for noise characterisation experiments that simultaneously estimates the Pauli error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise characterisation procedure. Then we demonstrate in circuit-level numerical simulation that this protocol is practically capable of calibrating a fast correlated matching decoder, enabling noise-aware decoding. We find that noise-aware decoding increases the error suppression factor of the code, leading to reductions in the logical error rate that increase exponentially with the code distance. Finally, we present several results obtained from experimentally implementing this protocol. We use the noise characterisation results to design an improved syndrome extraction circuit for a heavy hexagon memory that is adapted to the noise characteristics of the quantum device. The model error of our noise characterisation results suggests that the circuit-level Pauli noise model estimated by ACES can describe the essential features of quantum noise. We also operate a heavy hexagon memory and use noise estimates to predict performance and inform decoding. These results demonstrate that Pauli noise estimates can calibrate decoders to enable noise-aware decoding and inform the co-design of quantum error correcting codes, decoders, fault-tolerant circuits, and quantum devices.