Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2504.02673 · Quantum

QUITS: A modular Qldpc code circUIT Simulator

Mingyu Kang, Yingjia Lin, Hanwen Yao, Mert Gökduman, Arianna Meinking, Kenneth R. Brown

Published Dec 5, 2025• 1 citation
arXivHTMLPDF

Abstract

To achieve quantum fault tolerance with lower overhead, quantum low-density parity-check (QLDPC) codes have emerged as a promising alternative to topological codes such as the surface code, offering higher code rates. To support their study, an end-to-end framework for simulating QLDPC codes at the circuit level is needed. In this work, we present QUITS, a modular and flexible circuit-level simulator for QLDPC codes. Its design allows users to freely combine LDPC code constructions, syndrome extraction circuits, decoding algorithms, and noise models, enabling comprehensive and customizable studies of the performance of QLDPC codes under circuit-level noise. QUITS supports several leading QLDPC families, including hypergraph product codes, lifted product codes, and balanced product codes. As part of the framework, we introduce a syndrome extraction circuit improved from Tremblay, Delfosse, and Beverland [Phys. Rev. Lett. 129, 050504 (2022)] that applies to all three code families. In particular, for a small hypergraph product code, our circuit achieves lower depth than the conventional method, resulting in improved logical performance. Using QUITS, we evaluate the performance of state-of-the-art QLDPC codes and decoders under various settings, revealing trade-offs between the decoding runtime and the logical failure rate. The source code of QUITS is available online.

DOI
10.22331/q-2025-12-05-1931

Related papers

Time-Dynamic Circuits for Fault-Tolerant Shift Automorphisms in Quantum LDPC Codes

Younghun Kim, Spiro Gicev, Martin Sevior +1 more

Quantum low-density parity-check (qLDPC) codes have emerged as a promising approach for realizing low-overhead logical quantum memories. Recent theoretical developments have established shift automorphisms as a fundamental building block for completing the universal set of logical gates for qLDPC codes. However, practical challenges remain because the existing SWAP-based shift automorphism yields logical error rates that are orders of magnitude higher than those for fault-tolerant idle operations. In this work, we address this issue by dynamically varying the syndrome measurement circuits to implement the shift automorphisms without reducing the circuit distance. We benchmark our approach on both twisted and untwisted weight-6 generalized toric codes, including the gross code family. Our time-dynamic circuits for shift automorphisms achieve performance comparable to the idle operations under the circuit-level noise model (SI1000). Specifically, the dynamic circuits achieve more than an order of magnitude reduction in logical error rates relative to the SWAP-based scheme for the gross code at a physical error rate of $10^{-3}$, employing the BP-OSD decoder. Our findings improve both the error resilience and the time overhead of the shift automorphisms in qLDPC codes. Furthermore, our work can lead to alternative syndrome extraction circuit designs, such as leakage removal protocols, providing a practical pathway to utilizing dynamic circuits that extend beyond surface codes towards qLDPC codes.

quant-pharXiv:2601.09911•Jan 16, 2026•0 citations

Untangling QLDPC Codes with Biased Noise Ancilla

Runjiang Bi, Kathleen Chang, Shruti Puri

Remarkable technical progress has made high-rate, high-distance, quantum low-density parity-check codes (QLDPC) promising candidates for scalable quantum computing. However, it is hard to design low-depth syndrome extraction circuits that do not spread errors from ancilla qubits to multiple data qubits, also known as hook errors, for general QLDPC codes. Additionally, widely used decoders for these codes based on belief propagation are impaired due to short loops in the Tanner graph. Here, we investigate a hardware-aware approach to avoid these hooks and loops using biased noise ancillas. Using examples of bicycle bivariate codes and a cyclic hypergraph product code, which have been widely considered for practical application, we show that the effective fault-distance of the conventional syndrome extraction circuit can be significantly higher and the number of short loops can be significantly lower when the ancillas are subject to phase-flip errors only, compared to when they are also subject to bit-flip errors. This can result in almost an order of magnitude improvement in the logical error rate at circuit noise of $2\times 10^{-3}$ and when bit-flip errors in the ancilla are 50 times less likely than phase-flip errors. Our work demonstrates a significant and practical quantum error correction advantage with biased noise qubits in which full-bias cannot be maintained.

quant-pharXiv:2606.30592•Jun 30, 2026•0 citations

Optimal Compilation of Syndrome Extraction Circuits for General Quantum LDPC Codes

K Zhang, Dingchao Gao, Zhaohui Yang +4 more

Quantum error correcting codes (QECC) are essential for constructing large-scale quantum computers that deliver faithful results. As strong competitors to the conventional surface code, quantum low-density parity-check (qLDPC) codes are emerging rapidly: they offer high encoding rates while maintaining reasonable physical-qubit connectivity requirements. Despite the existence of numerous code constructions, a notable gap persists between these designs—some of which remain purely theoretical—and their circuit-level deployment.In this work, we propose Auto-Stabilizer-Check (ASC), a universal compilation framework that generates depth-optimal syndrome extraction circuits for arbitrary qLDPC codes. ASC leverages the sparsity of parity-check matrices and exploits the commutativity of X and Z stabilizer measurement subroutines to search for optimal compilation schemes. By iteratively invoking an SMT solver, ASC returns a depth-optimal solution if a satisfying assignment is found, and a near-optimal solution in cases of solver timeouts. Notably, ASC provides the first definitive answer to one of IBM’s open problems: for all instances of bivariate bicycle (BB) code reported in their work, our compiler certifies that no depth-6 syndrome extraction circuit exists.Furthermore, by integrating ASC with an end-to-end evaluation framework—one that assesses different compilation settings under a circuit-level noise model—ASC reduces circuit depth by approximately 50% and achieves an average 7x-8x suppression of the logical error rate for general qLDPC codes, compared with as-soon-as-possible (ASAP) and coloration-based scheduling. ASC thus substantially reduces manual design overhead and demonstrates its strong potential to serve as a key component in accelerating hardware deployment of qLDPC codes.

Design, Automation, and Test in Europe•Apr 20, 2026•0 citations

Optimal Compilation of Syndrome Extraction Circuits for General Quantum LDPC Codes

Kai Zhang, Dingchao Gao, Zhaohui Yang +4 more

Quantum error correcting codes (QECC) are essential for constructing large-scale quantum computers that deliver faithful results. As strong competitors to the conventional surface code, quantum low-density parity-check (qLDPC) codes are emerging rapidly: they offer high encoding rates while maintaining reasonable physical-qubit connectivity requirements. Despite the existence of numerous code constructions, a notable gap persists between these designs -- some of which remain purely theoretical -- and their circuit-level deployment. In this work, we propose Auto-Stabilizer-Check (ASC), a universal compilation framework that generates depth-optimal syndrome extraction circuits for arbitrary qLDPC codes. ASC leverages the sparsity of parity-check matrices and exploits the commutativity of X and Z stabilizer measurement subroutines to search for optimal compilation schemes. By iteratively invoking an SMT solver, ASC returns a depth-optimal solution if a satisfying assignment is found, and a near-optimal solution in cases of solver timeouts. Notably, ASC provides the first definitive answer to one of IBM's open problems: for all instances of bivariate bicycle (BB) code reported in their work, our compiler certifies that no depth-6 syndrome extraction circuit exists. Furthermore, by integrating ASC with an end-to-end evaluation framework -- one that assesses different compilation settings under a circuit-level noise model -- ASC reduces circuit depth by approximately 50% and achieves an average 7x-8x suppression of the logical error rate for general qLDPC codes, compared with as-soon-as-possible (ASAP) and coloration-based scheduling. ASC thus substantially reduces manual design overhead and demonstrates its strong potential to serve as a key component in accelerating hardware deployment of qLDPC codes.

quant-pharXiv:2603.21499•Mar 24, 2026•0 citations

Nonlocal resources for error correction in quantum low-density parity-check codes

Omprakash Chandra, Gopikrishnan Muraleedharan, Gavin K. Brennen

Quantum low-density parity-check (qLDPC) codes with high-performance and nonlocal stabilizers are an attractive alternative to the surface code because of their relatively high code rate and distance. However, unlike the surface code that has simple, geometrically local, stabilizer checks, qLDPC codes with nonlocal stabilizers are challenging to measure. Recent advances have shown how to deterministically perform high-fidelity, cavity-mediated many-body gates, enabling the encoding and decoding of nonlocal GHZ states. We show how to use this resource for constant-depth fault-tolerant stabilizer measurements in hypergraph product and lifted product codes. Using circuit-level noise simulations, including leakage and collective error from the noise-optimized cavity-mediated gate, we find promising thresholds of 0.84 % – 0.60 % for the hypergraph product code and pseudothreshold of 0.3 % – 0.4 % for the lifted product codes, with cavity cooperativities in the range C ∼ 10 4 – 10 6 . We propose a trilayer architecture, compatible with neutral atom platforms, which enhances circuit parallelizability.

arXiv:2409.05818•Physical Review Research•Aug 8, 2025•2 citations

Disassembling qLDPC codes for depth-optimal parity-check circuits

Minh T. P. Nguyen, Maximilian Rimbach-Russ, Stefano Bosco

Quantum low-density parity-check (qLDPC) codes offer a promising route to scalable fault-tolerant quantum computing, but their practical implementation requires efficient circuits for syndrome extraction. Many qLDPC families are assembled from a small set of components through explicit operations that imprint edge symmetries on their Tanner graphs. We show that disassembling the code by quotienting its symmetries one at a time, reduces parity-check circuit design to a much smaller problem acting only on the underlying components. Solutions to the reduced problem can then be lifted to the full code, yielding circuit constructions that apply to entire families of codes built from the same components. For lifted-product codes, our approach provides an optimal analytical construction for parity-check circuits achieving the lower bound on CNOT depth. We obtain analogous constructions for balanced-product codes and quantum--classical homological product codes. For quantum Tanner codes, the reduced problem is small enough to solve numerically, reaching the CNOT-depth lower bound for nearly all instance tested, including codes with up to 576 data qubits.

quant-pharXiv:2608.19917•Aug 21, 2026•0 citations
To achieve quantum fault tolerance with lower overhead, quantum low-density parity-check (QLDPC) codes have emerged as a promising alternative to topological codes such as the surface code, offering higher code rates. To support their study, an end-to-end framework for simulating QLDPC codes at the circuit level is needed. In this work, we present QUITS, a modular and flexible circuit-level simulator for QLDPC codes. Its design allows users to freely combine LDPC code constructions, syndrome extraction circuits, decoding algorithms, and noise models, enabling comprehensive and customizable studies of the performance of QLDPC codes under circuit-level noise. QUITS supports several leading QLDPC families, including hypergraph product codes, lifted product codes, and balanced product codes. As part of the framework, we introduce a syndrome extraction circuit improved from Tremblay, Delfosse, and Beverland [Phys. Rev. Lett. 129, 050504 (2022)] that applies to all three code families. In particular, for a small hypergraph product code, our circuit achieves lower depth than the conventional method, resulting in improved logical performance. Using QUITS, we evaluate the performance of state-of-the-art QLDPC codes and decoders under various settings, revealing trade-offs between the decoding runtime and the logical failure rate. The source code of QUITS is available online.
Quantum low-density parity-check (qLDPC) codes have emerged as a promising approach for realizing low-overhead logical quantum memories. Recent theoretical developments have established shift automorphisms as a fundamental building block for completing the universal set of logical gates for qLDPC codes. However, practical challenges remain because the existing SWAP-based shift automorphism yields logical error rates that are orders of magnitude higher than those for fault-tolerant idle operations. In this work, we address this issue by dynamically varying the syndrome measurement circuits to implement the shift automorphisms without reducing the circuit distance. We benchmark our approach on both twisted and untwisted weight-6 generalized toric codes, including the gross code family. Our time-dynamic circuits for shift automorphisms achieve performance comparable to the idle operations under the circuit-level noise model (SI1000). Specifically, the dynamic circuits achieve more than an order of magnitude reduction in logical error rates relative to the SWAP-based scheme for the gross code at a physical error rate of 10−310^{-3}10−3, employing the BP-OSD decoder. Our findings improve both the error resilience and the time overhead of the shift automorphisms in qLDPC codes. Furthermore, our work can lead to alternative syndrome extraction circuit designs, such as leakage removal protocols, providing a practical pathway to utilizing dynamic circuits that extend beyond surface codes towards qLDPC codes.
Remarkable technical progress has made high-rate, high-distance, quantum low-density parity-check codes (QLDPC) promising candidates for scalable quantum computing. However, it is hard to design low-depth syndrome extraction circuits that do not spread errors from ancilla qubits to multiple data qubits, also known as hook errors, for general QLDPC codes. Additionally, widely used decoders for these codes based on belief propagation are impaired due to short loops in the Tanner graph. Here, we investigate a hardware-aware approach to avoid these hooks and loops using biased noise ancillas. Using examples of bicycle bivariate codes and a cyclic hypergraph product code, which have been widely considered for practical application, we show that the effective fault-distance of the conventional syndrome extraction circuit can be significantly higher and the number of short loops can be significantly lower when the ancillas are subject to phase-flip errors only, compared to when they are also subject to bit-flip errors. This can result in almost an order of magnitude improvement in the logical error rate at circuit noise of 2×10−32\times 10^{-3}2×10−3 and when bit-flip errors in the ancilla are 50 times less likely than phase-flip errors. Our work demonstrates a significant and practical quantum error correction advantage with biased noise qubits in which full-bias cannot be maintained.
Quantum error correcting codes (QECC) are essential for constructing large-scale quantum computers that deliver faithful results. As strong competitors to the conventional surface code, quantum low-density parity-check (qLDPC) codes are emerging rapidly: they offer high encoding rates while maintaining reasonable physical-qubit connectivity requirements. Despite the existence of numerous code constructions, a notable gap persists between these designs—some of which remain purely theoretical—and their circuit-level deployment.In this work, we propose Auto-Stabilizer-Check (ASC), a universal compilation framework that generates depth-optimal syndrome extraction circuits for arbitrary qLDPC codes. ASC leverages the sparsity of parity-check matrices and exploits the commutativity of X and Z stabilizer measurement subroutines to search for optimal compilation schemes. By iteratively invoking an SMT solver, ASC returns a depth-optimal solution if a satisfying assignment is found, and a near-optimal solution in cases of solver timeouts. Notably, ASC provides the first definitive answer to one of IBM’s open problems: for all instances of bivariate bicycle (BB) code reported in their work, our compiler certifies that no depth-6 syndrome extraction circuit exists.Furthermore, by integrating ASC with an end-to-end evaluation framework—one that assesses different compilation settings under a circuit-level noise model—ASC reduces circuit depth by approximately 50% and achieves an average 7x-8x suppression of the logical error rate for general qLDPC codes, compared with as-soon-as-possible (ASAP) and coloration-based scheduling. ASC thus substantially reduces manual design overhead and demonstrates its strong potential to serve as a key component in accelerating hardware deployment of qLDPC codes.
Quantum error correcting codes (QECC) are essential for constructing large-scale quantum computers that deliver faithful results. As strong competitors to the conventional surface code, quantum low-density parity-check (qLDPC) codes are emerging rapidly: they offer high encoding rates while maintaining reasonable physical-qubit connectivity requirements. Despite the existence of numerous code constructions, a notable gap persists between these designs -- some of which remain purely theoretical -- and their circuit-level deployment. In this work, we propose Auto-Stabilizer-Check (ASC), a universal compilation framework that generates depth-optimal syndrome extraction circuits for arbitrary qLDPC codes. ASC leverages the sparsity of parity-check matrices and exploits the commutativity of X and Z stabilizer measurement subroutines to search for optimal compilation schemes. By iteratively invoking an SMT solver, ASC returns a depth-optimal solution if a satisfying assignment is found, and a near-optimal solution in cases of solver timeouts. Notably, ASC provides the first definitive answer to one of IBM's open problems: for all instances of bivariate bicycle (BB) code reported in their work, our compiler certifies that no depth-6 syndrome extraction circuit exists. Furthermore, by integrating ASC with an end-to-end evaluation framework -- one that assesses different compilation settings under a circuit-level noise model -- ASC reduces circuit depth by approximately 50% and achieves an average 7x-8x suppression of the logical error rate for general qLDPC codes, compared with as-soon-as-possible (ASAP) and coloration-based scheduling. ASC thus substantially reduces manual design overhead and demonstrates its strong potential to serve as a key component in accelerating hardware deployment of qLDPC codes.
Quantum low-density parity-check (qLDPC) codes with high-performance and nonlocal stabilizers are an attractive alternative to the surface code because of their relatively high code rate and distance. However, unlike the surface code that has simple, geometrically local, stabilizer checks, qLDPC codes with nonlocal stabilizers are challenging to measure. Recent advances have shown how to deterministically perform high-fidelity, cavity-mediated many-body gates, enabling the encoding and decoding of nonlocal GHZ states. We show how to use this resource for constant-depth fault-tolerant stabilizer measurements in hypergraph product and lifted product codes. Using circuit-level noise simulations, including leakage and collective error from the noise-optimized cavity-mediated gate, we find promising thresholds of 0.84 % – 0.60 % for the hypergraph product code and pseudothreshold of 0.3 % – 0.4 % for the lifted product codes, with cavity cooperativities in the range C ∼ 10 4 – 10 6 . We propose a trilayer architecture, compatible with neutral atom platforms, which enhances circuit parallelizability.
Quantum low-density parity-check (qLDPC) codes offer a promising route to scalable fault-tolerant quantum computing, but their practical implementation requires efficient circuits for syndrome extraction. Many qLDPC families are assembled from a small set of components through explicit operations that imprint edge symmetries on their Tanner graphs. We show that disassembling the code by quotienting its symmetries one at a time, reduces parity-check circuit design to a much smaller problem acting only on the underlying components. Solutions to the reduced problem can then be lifted to the full code, yielding circuit constructions that apply to entire families of codes built from the same components. For lifted-product codes, our approach provides an optimal analytical construction for parity-check circuits achieving the lower bound on CNOT depth. We obtain analogous constructions for balanced-product codes and quantum--classical homological product codes. For quantum Tanner codes, the reduced problem is small enough to solve numerically, reaching the CNOT-depth lower bound for nearly all instance tested, including codes with up to 576 data qubits.