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arXiv:2503.10935

Bias-preserving and error-detectable entangling operations in a superconducting dual-rail system

Mehta, Nitish, Teoh, James D., Taewan Noh, Agrawal, Ankur, Amos Anderson, Beau Birdsall, Avadh Brahmbhatt, Byrd, Winfred, Marc Cacioppo, Anthony Cabrera, Carroll, Leo, Jonathan Chen, Tzu-Chiao Chien, Richard Chamberlain, Jacob C. Curtis, Doreen Danso, Sanjana Renganatha Desigan, Francesco D'Acounto, Bassel Heiba Elfeky, S. M. Farzaneh, Foley, Chase, Benjamin Gudlewski, Hannah Hastings, Johnson, Robert, Nishaad Khedkar, Trevor Keen, Anup Kumar, Cihan Kurter, Kamila Krawczuk, Eric Langstengel, Richard D. Li, G. Liu, Hanyi Lu, Pinlei Lu, Luke Mastalli-Kelly, Adam Maines, Maxwell, Michael, Heather McCarrick, Mirzaei, Mona, A. Narla, Omar Rashad, Erik Reikes, Mizanur Rahman, Rurik A. Primiani, Schwaller, Michael, Sabbah, Ali, Tali Shemma, Aoshuang Shi, Satapathy, Sitakanta, Dean Stolpe, Jonathan Strenczewilk, Doug Szperka, Iu-Wei Sze, Sweeney, David, Preetham Chandra Tikkireddi, Chin-Lun Tsung, Daren Vet Sam, Weiss, Daniel K., Zhibo Yang, Liuqi Yu, Teng Zhang, Olivier Boireau, Horton, Stephen, Weinberg, Sean, José Aumentado, Bryan M. Cord, Chan U Lei, Joseph O’Connell Yuan, Shantanu Mundhada, Chou, Kevin S., Jr. Moseleley, Robert J. Schoelkopf

Published Mar 13, 2025• 0 citations
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Abstract

For useful quantum computation, error-corrected machines are required that can dramatically reduce the inevitable errors experienced by physical qubits. While significant progress has been made in approaching and exceeding the surface-code threshold in superconducting platforms, large gains in the logical error rate with increasing system size remain out of reach. This is due both to the large number of required physical qubits and the need to operate far below threshold. Importantly, by exploiting the biases and structure of the physical errors, this threshold can be raised. Erasure qubits achieve this by detecting certain errors at the hardware level. Dual-rail qubits encoded in superconducting cavities are a promising erasure qubit wherein the dominant error, photon loss, can be detected and converted to an erasure. In these approaches, the complete set of operations, including two qubit gates, must be high performance and preserve as much of the desirable hierarchy or bias in the errors as possible. Here, we design and realize a novel two-qubit gate for dual-rail erasure qubits based on superconducting microwave cavities. The gate is high-speed ($\sim$500 ns duration), and yields a residual gate infidelity after error detection below 0.1%. Moreover, we experimentally demonstrate that this gate largely preserves the favorable error structure of idling dual-rail qubits, making it ideal for error correction. We measure low erasure rates of $\sim$0.5% per gate, as well as low and asymmetric dephasing errors that occur at least three times more frequently on control qubits compared to target qubits. Bit-flip errors are practically nonexistent, bounded at the few parts per million level. This error asymmetry has not been well explored but is extremely useful in quantum error correction and flag-qubit contexts, where it can create a faster path to effective error-corrected systems.

DOI
10.48550/arxiv.2503.10935

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For useful quantum computation, error-corrected machines are required that can dramatically reduce the inevitable errors experienced by physical qubits. While significant progress has been made in approaching and exceeding the surface-code threshold in superconducting platforms, large gains in the logical error rate with increasing system size remain out of reach. This is due both to the large number of required physical qubits and the need to operate far below threshold. Importantly, by exploiting the biases and structure of the physical errors, this threshold can be raised. Erasure qubits achieve this by detecting certain errors at the hardware level. Dual-rail qubits encoded in superconducting cavities are a promising erasure qubit wherein the dominant error, photon loss, can be detected and converted to an erasure. In these approaches, the complete set of operations, including two qubit gates, must be high performance and preserve as much of the desirable hierarchy or bias in the errors as possible. Here, we design and realize a novel two-qubit gate for dual-rail erasure qubits based on superconducting microwave cavities. The gate is high-speed (∼\sim∼500 ns duration), and yields a residual gate infidelity after error detection below 0.1%. Moreover, we experimentally demonstrate that this gate largely preserves the favorable error structure of idling dual-rail qubits, making it ideal for error correction. We measure low erasure rates of ∼\sim∼0.5% per gate, as well as low and asymmetric dephasing errors that occur at least three times more frequently on control qubits compared to target qubits. Bit-flip errors are practically nonexistent, bounded at the few parts per million level. This error asymmetry has not been well explored but is extremely useful in quantum error correction and flag-qubit contexts, where it can create a faster path to effective error-corrected systems.
Quantum error correction (QEC) will likely be required to realize the full potential of quantum computing, but comes with daunting hardware overheads and demands low gate errors on the physical qubits1–4. These requirements can be eased by engineering qubits with a strong error hierarchy, in which the most common noise channels are also the easiest to correct. Erasure qubits can achieve this when detectable leakage errors out of the computational subspace dominate over the residual Pauli errors5–11, resulting in higher thresholds and improved scaling with code distance5,12,13. In practice, these advantages come to fruition only if the error hierarchy is preserved as much as possible throughout all gates and operations. Here we design and realize a two-qubit entangling gate for dual-rail cavity qubits, a type of erasure qubit encoded in a pair of superconducting microwave cavities7. Our experimental demonstration confirms that the error hierarchy is largely preserved during the gate. The gate is fast (about 500 ns duration) and shows low erasure rates of approximately 0.5% per gate, remaining Pauli errors below 0.1%, and a strong bias towards dephasing errors, in which bit-flips are practically non-existent at the 10−6 level. These results enable a faster path to error-corrected systems that rapidly suppress errors as they scale; a claim we support with our detailed surface code simulations. A fast, low-error entangling gate for dual-rail cavity erasure qubits preserves a strong error hierarchy, advancing scalable quantum error correction with substantially improved fault-tolerant performance.
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Erasure qubits are beneficial for quantum error correction due to their relaxed threshold requirements. While dual-rail erasure qubits have been demonstrated with a strong error hierarchy in circuit quantum electrodynamics, biased-erasure qubits -- where erasures originate predominantly from one logical basis state -- offer further advantages. Here, we realize a hardware-efficient biased-erasure qubit encoded in the vacuum and two-photon Fock states of a single microwave cavity. The qubit exhibits an erasure bias ratio of over 265. By using a transmon ancilla for logical measurements and mid-circuit erasure detections, we achieve logical state assignment errors below 1% and convert over 99.3% leakage errors into detected erasures. After postselection against erasures, we achieve effective logical relaxation and dephasing rates of (6.2 ms)−1(6.2~\mathrm{ms})^{-1}(6.2 ms)−1 and (3.1 ms)−1(3.1~\mathrm{ms})^{-1}(3.1 ms)−1, respectively, which exceed the erasure error rate by factors of 31 and 15, establishing a strong error hierarchy within the logical subspace. These postselected error rates indicate a coherence gain of about 6.0 beyond the break-even point set by the best physical qubit encoded in the two lowest Fock states in the cavity. Moreover, randomized benchmarking with interleaved erasure detections reveals a residual logical gate error of 0.29%. This work establishes a compact and hardware-efficient platform for biased-erasure qubits, promising concatenations into outer-level stabilizer codes toward fault-tolerant quantum computation.
The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computation. To this end, we introduce the circuit-Quantum Electrodynamics (QED) dual-rail qubit in which our physical qubit is encoded in the single-photon subspace, [Formula: see text], of two superconducting microwave cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are in general much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers unique capabilities. Using just one additional transmon ancilla per dual-rail qubit, we describe how to perform a gate-based set of universal operations that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors in the cavities and the transmon can be detected and converted to erasure errors in all operations, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit exhibits a favorable hierarchy of error rates and is expected to perform well below the relevant QEC thresholds with today's coherence times.
Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states ∣0L⟩\ket{0_\text{L}}∣0L​⟩ and ∣1L⟩\ket{1_\text{L}}∣1L​⟩ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit T1T_1T1​ lifetime exceeding 500 μs500\,μ\mathrm{s}500μs, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the T1T_1T1​ time of the transmon physical qubit. Coherence times beyond 300 μs300\,μ\mathrm{s}300μs are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of 10−410^{-4}10−4. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.
Erasure qubits -- qubits designed to have an error profile that is dominated by detectable leakage errors -- are a promising way to cut down the resources needed for quantum error correction. There have been several recent experiments demonstrating erasure qubits in superconducting quantum processors, most notably the dual-rail qubit defined by the one-photon subspace of two coupled cavities. An outstanding challenge is that the ancillary transmons needed to facilitate erasure checks and two-qubit gates introduce a substantial amount of noise, limiting the benefits of working with erasure-biased qubits. Here, we show how to suppress the adverse effects of transmon-induced noise while performing erasure checks or two-qubit gates. We present control schemes for these operations that suppress erasure check errors by three orders of magnitude and reduce the logical two-qubit gate infidelities by up to three orders of magnitude.