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arXiv:2307.03169

Demonstrating a superconducting dual-rail cavity qubit with erasure-detected logical measurements

Chou, Kevin S., Tali Shemma, Heather McCarrick, Tzu-Chiao Chien, James D. Teoh, Patrick Winkel, Amos Anderson, Chen, Jonathan, Jacob C. Curtis, Stijn J. de Graaf, John W. O. Garmon, Benjamin Gudlewski, William D. Kalfus, Trevor Keen, Nishaad Khedkar, Chan U Lei, Gangqiang Liu, Pinlei Lu, Yao Lu, Aniket Maiti, Luke Mastalli-Kelly, Mehta, Nitish, Shantanu Mundhada, A. Narla, Taewan Noh, Takahiro Tsunoda, Sophia H. Xue, Joseph O’Connell Yuan, Luigi Frunzio, José Aumentado, Shruti Puri, S. M. Girvin, Jr. Moseley, Robert J. Schoelkopf

Published Jul 6, 2023• 3 citations
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Abstract

A critical challenge in developing scalable error-corrected quantum systems is the accumulation of errors while performing operations and measurements. One promising approach is to design a system where errors can be detected and converted into erasures. Such a system utilizing erasure qubits are known to have relaxed requirements for quantum error correction. A recent proposal aims to do this using a dual-rail encoding with superconducting cavities. However, experimental characterization and demonstration of a dual-rail cavity qubit has not yet been realized. In this work, we implement such a dual-rail cavity qubit; we demonstrate a projective logical measurement with integrated erasure detection and use it to measure dual-rail qubit idling errors. We measure logical state preparation and measurement errors at the $0.01\%$-level and detect over $99\%$ of cavity decay events as erasures. We use the precision of this new measurement protocol to distinguish different types of errors in this system, finding that while decay errors occur with probability $\sim 0.2\%$ per microsecond, phase errors occur 6 times less frequently and bit flips occur at least 140 times less frequently. These findings represent the first confirmation of the expected error hierarchy necessary to concatenate dual-rail erasure qubits into a highly efficient erasure code.

DOI
10.48550/arxiv.2307.03169

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A critical challenge in developing scalable error-corrected quantum systems is the accumulation of errors while performing operations and measurements. One promising approach is to design a system where errors can be detected and converted into erasures. Such a system utilizing erasure qubits are known to have relaxed requirements for quantum error correction. A recent proposal aims to do this using a dual-rail encoding with superconducting cavities. However, experimental characterization and demonstration of a dual-rail cavity qubit has not yet been realized. In this work, we implement such a dual-rail cavity qubit; we demonstrate a projective logical measurement with integrated erasure detection and use it to measure dual-rail qubit idling errors. We measure logical state preparation and measurement errors at the 0.01%0.01\%0.01%-level and detect over 99%99\%99% of cavity decay events as erasures. We use the precision of this new measurement protocol to distinguish different types of errors in this system, finding that while decay errors occur with probability ∼0.2%\sim 0.2\%∼0.2% per microsecond, phase errors occur 6 times less frequently and bit flips occur at least 140 times less frequently. These findings represent the first confirmation of the expected error hierarchy necessary to concatenate dual-rail erasure qubits into a highly efficient erasure code.
For useful quantum computation, error-corrected machines are required that can dramatically reduce the inevitable errors experienced by physical qubits. While significant progress has been made in approaching and exceeding the surface-code threshold in superconducting platforms, large gains in the logical error rate with increasing system size remain out of reach. This is due both to the large number of required physical qubits and the need to operate far below threshold. Importantly, by exploiting the biases and structure of the physical errors, this threshold can be raised. Erasure qubits achieve this by detecting certain errors at the hardware level. Dual-rail qubits encoded in superconducting cavities are a promising erasure qubit wherein the dominant error, photon loss, can be detected and converted to an erasure. In these approaches, the complete set of operations, including two qubit gates, must be high performance and preserve as much of the desirable hierarchy or bias in the errors as possible. Here, we design and realize a novel two-qubit gate for dual-rail erasure qubits based on superconducting microwave cavities. The gate is high-speed ($\sim$500 ns duration), and yields a residual gate infidelity after error detection below 0.1%. Moreover, we experimentally demonstrate that this gate largely preserves the favorable error structure of idling dual-rail qubits, making it ideal for error correction. We measure low erasure rates of $\sim$0.5% per gate, as well as low and asymmetric dephasing errors that occur at least three times more frequently on control qubits compared to target qubits. Bit-flip errors are practically nonexistent, bounded at the few parts per million level. This error asymmetry has not been well explored but is extremely useful in quantum error correction and flag-qubit contexts, where it can create a faster path to effective error-corrected systems.
Qubits with predominantly erasure errors present distinctive advantages for quantum error correction (QEC) and fault-tolerant quantum computing. Logical qubits based on dual-rail encoding that exploit erasure detection have been recently proposed in superconducting circuit architectures, with either coupled transmons or cavities. Here, we implement a dual-rail qubit encoded in a compact, double-post superconducting cavity. Using an auxiliary transmon, we perform erasure detection on the dual-rail subspace. We characterize the behavior of the code space by a novel method to perform joint-Wigner tomography. This is based on modifying the cross-Kerr interaction between the cavity modes and the transmon. We measure an erasure rate of 3.981±0.003 (ms)^{-1} and a residual, postselected dephasing error rate up to 0.17 (ms)^{-1} within the code space. This strong hierarchy of error rates, together with the compact and hardware-efficient nature of this novel architecture, holds promise in realizing QEC schemes with enhanced thresholds and improved scaling.
Erasure qubits are beneficial for quantum error correction due to their relaxed threshold requirements. While dual-rail erasure qubits have been demonstrated with a strong error hierarchy in circuit quantum electrodynamics, biased-erasure qubits -- where erasures originate predominantly from one logical basis state -- offer further advantages. Here, we realize a hardware-efficient biased-erasure qubit encoded in the vacuum and two-photon Fock states of a single microwave cavity. The qubit exhibits an erasure bias ratio of over 265. By using a transmon ancilla for logical measurements and mid-circuit erasure detections, we achieve logical state assignment errors below 1% and convert over 99.3% leakage errors into detected erasures. After postselection against erasures, we achieve effective logical relaxation and dephasing rates of (6.2 ms)−1(6.2~\mathrm{ms})^{-1}(6.2 ms)−1 and (3.1 ms)−1(3.1~\mathrm{ms})^{-1}(3.1 ms)−1, respectively, which exceed the erasure error rate by factors of 31 and 15, establishing a strong error hierarchy within the logical subspace. These postselected error rates indicate a coherence gain of about 6.0 beyond the break-even point set by the best physical qubit encoded in the two lowest Fock states in the cavity. Moreover, randomized benchmarking with interleaved erasure detections reveals a residual logical gate error of 0.29%. This work establishes a compact and hardware-efficient platform for biased-erasure qubits, promising concatenations into outer-level stabilizer codes toward fault-tolerant quantum computation.
Qubits that experience predominantly erasure errors offer distinct advantages for fault-tolerant operation. Indeed, dual-rail encoded erasure qubits in superconducting cavities and transmons have demonstrated high-fidelity operations by converting physical-qubit relaxation into logical-qubit erasures, but this comes at the cost of increased hardware overhead and circuit complexity. Here, we address these limitations by realizing erasure conversion in a single fluxonium operated at zero flux, where the logical state is encoded in its 0-2 subspace. A single, carefully engineered resonator provides both mid-circuit erasure detection and end-of-line (EOL) logical measurement. Post-selection on non-erasure outcomes results in more than four-fold increase of the logical lifetime, from 193 μ193~μ193 μs to 869 μ869~μ869 μs. Finally, we characterize measurement-induced logical dephasing as a function of measurement power and frequency, and infer that each erasure check contributes a negligible error of 7.2×10−57.2\times 10^{-5}7.2×10−5. These results establish integer-fluxonium as a promising, resource-efficient platform for erasure-based error mitigation, without requiring additional hardware.
The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computation. To this end, we introduce the circuit-Quantum Electrodynamics (QED) dual-rail qubit in which our physical qubit is encoded in the single-photon subspace, [Formula: see text], of two superconducting microwave cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are in general much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers unique capabilities. Using just one additional transmon ancilla per dual-rail qubit, we describe how to perform a gate-based set of universal operations that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors in the cavities and the transmon can be detected and converted to erasure errors in all operations, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit exhibits a favorable hierarchy of error rates and is expected to perform well below the relevant QEC thresholds with today's coherence times.
Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers.