One of the critical challenges solid-state quantum processors face is the presence of fabrication imperfections and two-level systems, which render certain qubits and gates either inoperable or much noisier than tolerable by quantum error-correction protocols. To address this challenge, we develop a suite of novel and highly performant methods for adapting surface code patches in the presence of defective qubits and gates, which we call . We explain how our algorithm generates and compares several strategies in order to find the optimal one for any given configuration of defective components, as well as introduce heuristics to improve runtime and minimize computing resources required by our algorithm. In addition to memory storage we also show how to apply our methods to lattice surgery protocols. Compared to prior works, our methods significantly improve the code distance of the adapted surface code patches for realistic defect rates, resulting in a logical performance similar to that of the defect-free patches.
One of the critical challenges solid-state quantum processors face is the presence of fabrication imperfections and two-level systems, which render certain qubits and gates either inoperable or much noisier than tolerable by quantum error-correction protocols. To address this challenge, we develop a suite of novel and highly performant methods for adapting surface code patches in the presence of defective qubits and gates, which we call . We explain how our algorithm generates and compares several strategies in order to find the optimal one for any given configuration of defective components, as well as introduce heuristics to improve runtime and minimize computing resources required by our algorithm. In addition to memory storage we also show how to apply our methods to lattice surgery protocols. Compared to prior works, our methods significantly improve the code distance of the adapted surface code patches for realistic defect rates, resulting in a logical performance similar to that of the defect-free patches.
Whether it is at the fabrication stage or during the course of the quantum computation, e.g. because of high-energy events like cosmic rays, the qubits constituting an error correcting code may be rendered inoperable. Such defects may correspond to individual qubits or to clusters and could potentially disrupt the code sufficiently to generate logical errors. In this paper, we explore a novel a d a p t i v e approach for surface code quantum error correction on a defective lattice. We show that combining an appropriate defect detection algorithm and a quarantine of the identified zone allows one to preserve the advantage of quantum error correction at finite code sizes, at the cost of a qubit overhead that scales with the size of the defect. Our numerics indicate that the code's threshold need not be significantly affected; for example, for a certain scenario where small defects repeatedly arise in each logical qubit, the noise threshold is 2.7 % (versus the defect-free case of 2.9 % ). These results pave the way to the experimental implementation of large-scale quantum computers where defects will be inevitable.
To make practical quantum algorithms work, large-scale quantum processors protected by error-correcting codes are required to resist noise and ensure reliable computational outcomes. However, a major challenge arises from defects in processor fabrication, as well as occasional losses or cosmic rays during the computing process, all of which can lead to qubit malfunctions and disrupt error-correcting codes’ normal operations. In this context, we introduce an automatic adapter to implement the surface code on defective lattices. Unlike previous approaches, this adapter leverages newly proposed bandage-like super-stabilizers to save more qubits when defects are clustered, thus enhancing the code distance and reducing super-stabilizer weight. For instance, in comparison with earlier methods, with a code size of 27 and a random defect rate of 2%, the disabled qubits decrease by 1/3, and the average preserved code distance increases by 63%. This demonstrates a significant reduction in overhead when handling defects using our approach, and this advantage amplifies with increasing processor size and defect rates. Our work presents a low-overhead, automated solution to the challenge of adapting the surface code to defects, an essential step towards scaling up the construction of large-scale quantum computers for practical applications.
Defect-adaptive surface-code methods construct valid logical patches on imperfect hardware, but fault-tolerant computation also requires certifying that requested logical operations remain executable on the resulting irregular geometries. We address this problem for lattice-surgery merges whose interfaces intersect deformed boundaries, unavailable checks, or gauge-inferred operators. Our compiler constructs an admissible seam-measurement set whose elements associate effective seam supports with raw-outcome selectors and schedule metadata. A GF(2) row-space test then determines whether the requested joint parity is realizable modulo pre-merge stabilizer constraints, returning either an explicit parity-extraction rule or a dual witness of non-realizability within the evaluated set. Paired ablations isolate the contribution of the proposed measurement-set construction rules. We further apply the test to configurations generated by Snakes and Ladders (SnL) on 15,000 clustered boundary-defect maps. Adding the proposed boundary-reconstruction rows increases the certification rate from 61.88\% to 62.79\%, with the gain concentrated in strongly clustered regimes. The framework therefore provides a compiler step that separates defect-adaptive patch construction from the certification and extraction of lattice-surgery parity measurements.
When calculating the overhead of a quantum algorithm made fault-tolerant using the surface code, many previous works have used defects and braids for logical qubit storage and state distillation. In this work, we show that lattice surgery reduces the storage overhead by over a factor of 4, and the distillation overhead by nearly a factor of 5, making it possible to run algorithms with 108 T gates using only 3.7×105 physical qubits capable of executing gates with error p∼10−3. These numbers strongly suggest that defects and braids in the surface code should be deprecated in favor of lattice surgery.
Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.
A solid-state quantum-computing architecture will require the fabrication of arrays of many coupled qubits. It is inevitable that this process will produce qubits and couplers with varying performance, with some components underperforming due to imperfect fabrication. Quantum error-correction requires high-performing components and hence these defects must be dealt with, either by adapting the code to exclude the defects, or by informing the decoder to accommodate defects in post-processing. Here we implement and compare strategies to operate distance-5 surface codes on a quantum processor consisting of a square-lattice array of 120 superconducting qubits. We demonstrate a dramatic reduction in the probability of a logical error in a memory experiment by excluding underperforming components, compared with both a standard approach of ignoring defects, and a defect-aware decoding approach. We observe up to 2.8X improvement in logical errors per round when excluding defects compared with the standard defect-ignorant approach (1.62% compared to 4.49%). In contrast, defect-aware decoding gives only modest gains. Defects are also expected to be particularly harmful for measurement-based logical operations. Using a stability experiment we show that excluding defects resurrects measurement-based logic gate performance, observing a 6.3% per-round suppression of failure rate when excluding defects, compared to zero suppression otherwise. Furthermore, we show a further substantial decrease in logical errors when using leakage post-selection in combination with our defect exclusion strategies, resulting in a distance-5 code outperforming the best distance-3 in one basis. Our experiments therefore give a proof-of-principle demonstration of the essential utility of defect exclusion methods in the scale-up of solid-state quantum computing approaches.