One of the most important and topical challenges of quantum circuits is their scalability. Rapid single flux quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. By condensing the control and readout to single-flux-quantum-based on-chip devices that are directly connected to the quantum systems, it is possible to minimize the total system overhead, improving scalability and integration. In this article, we present a novel RSFQ device that generates multitone digital signals, based on complex pulse train sequences using a circular shift register (CSR) and a comb filter stage. We show that the frequency spectrum of the pulse trains is dependent on a preloaded pattern on the CSR, as well as on the delay line of the comb filter stage. By carefully selecting both the pattern and delay, the desired tones can be isolated and amplified as required. Finally, we propose architectures where this device can be implemented to control and read out arrays of quantum devices, such as qubits and single-photon detectors.
One of the most important and topical challenges of quantum circuits is their scalability. Rapid single flux quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. By condensing the control and readout to single-flux-quantum-based on-chip devices that are directly connected to the quantum systems, it is possible to minimize the total system overhead, improving scalability and integration. In this article, we present a novel RSFQ device that generates multitone digital signals, based on complex pulse train sequences using a circular shift register (CSR) and a comb filter stage. We show that the frequency spectrum of the pulse trains is dependent on a preloaded pattern on the CSR, as well as on the delay line of the comb filter stage. By carefully selecting both the pattern and delay, the desired tones can be isolated and amplified as required. Finally, we propose architectures where this device can be implemented to control and read out arrays of quantum devices, such as qubits and single-photon detectors.
We present a new design of a Rapid Single-Flux-Quantum (RSFQ) all-digital one-bit autocorrelator for submillimeter spectrometry applications, featuring 4 GHz input signal bandwidth, double oversampling quantizer, and 16 Mbps-per-channel output rate. The delay line of the autocorrelator is based on a circular shift register with XOR gates performing multiplication of the delayed and undelayed single-bit signals at every stage. The multiplication results are accumulated by room-temperature electronics after being prescaled in on-chip binary counters consisting of 10 T flip-flops per stage. We report results of experimental testing of a 16-stage autocorrelator delay line with multiplication and for a linear array of 8 low-power T flip-flop binary counters, all fabricated in HYPRES' standard 3.5 /spl mu/m 1000 A/cm/sup 2/ Nb-trilayer process. We also discuss physical and technical limits of the minimal power dissipation in RSFQ circuits.
We describe recent topics of rapid-single-flux-quantum (RSFQ) circuits. Much higher integration and higher-speed operation are required for commercializing the RSFQ circuits in any application. To satisfy this requirement, we measure several kinds of time fluctuations that possibly limit the integration level and operating speed, and introduce the flexible passive transmission line technology including a multicasting transmitter. In addition, we describe our ongoing applications. A multiple-detectors-system is expected to open a new application field of an RSFQ-based analog-to-digital converter and a digital signal processor. As for a microprocessor application, increased number of arithmetic logic units may be effective for enhancing the computing performances.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
The convergence of quantum computing and high-performance computing (HPC) necessitates innovative approaches to qubit control and coherence for scalable quantum systems. In this work, we explore the integration of superconducting Single-Flux Quantum (SFQ) digital circuits to enhance quantum state manipulation, leveraging their potential for high-speed, energy-efficient classical control. Our approach maps SFQ pulse trains and configurable SFQ-based switches to discrete phase shifts, enabling efficient qubit state transformations with minimal decoherence overhead. We introduce a classically driven SFQ-based quantum gate implementation, where SFQ pulses orchestrate the state evolution of qubits. To support dynamic and flexible qubit control within hybrid quantum-HPC architectures, we design and implement a multi-frequency SFQ pulse generator, capable of generating tailored pulse sequences that seamlessly interface with SQUID-based resonator-qubit cavities. This work demonstrates a promising path toward integrating quantum accelerators with classical HPC infrastructure, opti-mizing quantum-classical workflows, and enabling scalable, high-performance quantum computation.
The growing market for fast floating-point coprocessors, digital signal processing chips, and graphics processors has created a demand for high speed, area efficient multipliers. Current architectures range from small, low-performance shift and add multipliers, to large, high-performance array and tree multipliers. Conventional linear array multipliers achieve high performance in a regular structure, but require large amounts of silicon. Tree structures achieve even higher performance than linear arrays but the tree interconnection is more complex and less regular, making them even larger than linear arrays. Ideally, one would want the speed benefits of a tree structure, the regularity of an array multiplier, and the small size of a shift and add multiplier. In electronics, rapid single flux quantum (RSFQ) is a digital electronics technology that relies on quantum effects in superconducting devices, namely Josephson junctions, to process digital signals. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor electronics. However, RSFQ is not a quantum computing technology in the traditional sense. Even so, RSFQ is very different from the traditional CMOS transistor technology used in every day computers due to its power efficiency and high speed it is being used.
Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology.>