This article proposes two quantum operation scheduling methods for accelerating parallel state-vector-based quantum circuit simulation using multiple graphics processing units (GPUs). The proposed methods reduce all-to-all communication caused by qubit reordering, which can dominate the overhead of parallel simulation. Our out-of-order approach eliminates redundant reorderings by introducing intentional delays in reordering communications such that multiple reorderings can be aggregated into a single reordering. The delays are carefully introduced based on the principles of time-space tiling, or a cache optimization technique for classical computers, which we use to arrange the execution order of quantum operations. Moreover, we develop these methods tailored for two primary procedures in variational quantum eigensolver simulation: quantum state update (QSU) and expectation value computation (EVC). Our QSU simulation takes an advantage of the hierarchical interconnection of GPU systems to avoid slow inter-node communication. On the other hand, our EVC simulation reduces the number of reorderings by diagonalization of Pauli strings. Experimental validation on 32-GPU executions demonstrates acceleration in QSU and EVC—up to 54× and 1,657×, respectively—compared to an inorder-based method. We believe that our out-of-order approach is useful for accelerating large-scale quantum circuit simulations, including QSU and/or EVC that operate qubits in a regular manner.
This article proposes two quantum operation scheduling methods for accelerating parallel state-vector-based quantum circuit simulation using multiple graphics processing units (GPUs). The proposed methods reduce all-to-all communication caused by qubit reordering, which can dominate the overhead of parallel simulation. Our out-of-order approach eliminates redundant reorderings by introducing intentional delays in reordering communications such that multiple reorderings can be aggregated into a single reordering. The delays are carefully introduced based on the principles of time-space tiling, or a cache optimization technique for classical computers, which we use to arrange the execution order of quantum operations. Moreover, we develop these methods tailored for two primary procedures in variational quantum eigensolver simulation: quantum state update (QSU) and expectation value computation (EVC). Our QSU simulation takes an advantage of the hierarchical interconnection of GPU systems to avoid slow inter-node communication. On the other hand, our EVC simulation reduces the number of reorderings by diagonalization of Pauli strings. Experimental validation on 32-GPU executions demonstrates acceleration in QSU and EVC—up to 54× and 1,657×, respectively—compared to an inorder-based method. We believe that our out-of-order approach is useful for accelerating large-scale quantum circuit simulations, including QSU and/or EVC that operate qubits in a regular manner.
Quantum computers are becoming practical for computing numerous applications. However, simulating quantum computing on classical computers is still demanding yet useful because current quantum computers are limited because of computer resources, hardware limits, instability, and noises. Improving quantum computing simulation performance in classical computers will contribute to the development of quantum computers and their algorithms. Quantum computing simulations on classical computers require long performance times, especially for quantum circuits with a large number of qubits or when simulating a large number of shots for noise simulations or circuits with intermediate measures. Graphical processing units (GPU) are suitable to accelerate quantum computer simulations by exploiting their computational power and high bandwidth memory and they have a large advantage in simulating relatively larger qubits circuits. However, GPUs are inefficient at simulating multi-shots runs with noises because the randomness prevents highly parallelization. In addition, GPUs have a disadvantage in simulating circuits with a small number of qubits because of the large overheads in GPU kernel execution. In this paper, we introduce optimization techniques for multi-shot simulations on GPUs. We gather multiple shots of simulations into a single GPU kernel execution to reduce overheads by scheduling randomness caused by noises. In addition, we introduce shot-branching that reduces calculations and memory usage for multi-shot simulations. By using these techniques, we speed up x10 from previous implementations.
Simulating quantum many-body dynamics is important both for fundamental understanding of physics and practical applications for quantum information processing. Therefore, classical simulation methods have been developed so far. Specifically, the Trotter-Suzuki decomposition can analyze a highly complex quantum dynamics, if the number of qubits is sufficiently small so that main memory can store the state vector. However, simulation of quantum dynamics via Trotter-Suzuki decomposition requires a huge number of steps, each of which accesses the state vector, and hence the simulation time becomes impractically long. To settle this issue, we propose a technique to accelerate simulation of quantum dynamics via simultaneous diagonalization of mutually commuting Pauli groups, which is also attracting a lot of attention to reduce the measurement overheads in quantum algorithms. We group the Hamiltonian into mutually commuting Pauli strings, and each of them is diagonalized in the computational basis via a Clifford transformation. Since diagonal operators are applied on the state vector simultaneously with minimum memory access, this method successfully uses performance of highly parallel processors such as Graphics Processing Units (GPU). Compared to both CPU and GPU implementations using fast quantum circuit simulator “qulacs,” the numerical experiments have shown that our method provides a few tens of times acceleration.
Simulating the behavior of quantum circuits on classical computers is one of the widely used approaches for current quantum computing device and quantum algorithm research. State- vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in significant memory access and communication overhead far longer than calculation time. Consequently, data communication time often becomes the primary bottleneck in quantum circuit simulation. Many classical simulators, such as QuEST, are designed to execute quantum gates serially without exploiting data locality, and all amplitudes need to be exchanged. Such a gate-unaware full-data communication scheme forces powerful computation such as GPUs to spend substantial time waiting for data transfers. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. We analyze the on-demand communication process and develop a communication cost model to elucidate the relationship between communication costs and circuit partition. Since greedy circuit partition method can only yield locally optimal solutions, we propose a choice-start-node quantum circuit partition method guided by the communication cost model to further reduce communication overhead in quantum circuit simulation. We evaluate on a 4-node cluster with 2 NVIDIA A100 GPUs on each node and our design achieves 59.32× speedup compared to the gate-unaware full-data communication scheme. Furthermore, compared to the greedy circuit partition method, our partition method can achieve simulation acceleration of 1.79×.
The classical simulation of quantum algorithms is a crucial tool for circuit development, testing, and validation. Although acceleration using GPUs significantly reduces simulation time, most high-performance simulators rely on vendor-specific frameworks that target data-center hardware. To broaden access to quantum simulation, this work proposes a vendor-agnostic approach targeting the integrated GPUs commonly found in consumer-grade laptops. A primary challenge in state-vector simulation is its inherently poor spatial locality, which creates a memory bandwidth bottleneck. Consequently, baseline implementations experience a severe degradation in relative GPU speedup as the number of simulated qubits increases. To address this limitation, we introduce a state partitioning optimization that reorganizes the quantum state vector to maximize the last-level cache locality and minimize costly main memory fetches. We evaluate this strategy using a Quantum Phase Estimation algorithm across diverse architectures from Intel, AMD, and Apple. The experimental results demonstrate that the proposed optimization successfully mitigates performance degradation at larger qubit scales. In particular, for a 28-qubit simulation, the optimization reversed a performance deficit on an Intel Core i5, improving the GPU speedup over the CPU from 0.95x to 1.89x, and increased the Apple M1 Pro speedup from 3.71x to 5.88x. Overall, this approach yields consistent execution time improvements, demonstrating the viability of integrated GPUs for efficient quantum circuit simulation.
This article presents a comprehensive study of the performance of quantum circuit simulation using the Matrix Product State (MPS) method within Qiskit Aer. The primary focus is on comparing the computational efficiency of implementations on central processing unit (CPU) and graphics processing unit (GPU) across various simulation platforms. Four key quantum algorithms are experimentally examined: the Variational Quantum Eigensolver (VQE), the Quantum Fourier Transform (QFT), the Quantum Approximate Optimization Algorithm (QAOA), and the Greenberger– Horne–Zeilinger (GHZ) state. For each algorithm, graphs are constructed showing the dependence of execution time on the number of qubits and the type of simulator. A single diagram is also provided to compare all four algorithms using the MPS method in Qiskit Aer. The results indicate that although the MPS simulator in Qiskit Aer is currently implemented only for CPU, it outperforms the traditional statevector simulator for low-entanglement circuits. At the same time, the lack of GPU acceleration limits the scalability of the MPS simulator. Analysis shows that implementing hardware acceleration of SVD operations using NVIDIA's cuQuantum and cuTensorNet libraries can provide a speedup of up to seven times. A comparative analysis of GPU implementations in Qiskit Aer and CUDA-Q is also conducted, including libraries such as cuStateVec, LAPACK, and cuSOLVER. Graphs are created to demonstrate the strengths and weaknesses of the simulators and simulation methods in Qiskit Aer. Notably, the MPS method remains one of the fastest by computation speed on CPU, but is sometimes surpassed by other methods on GPU. Further optimization directions for MPS are proposed, including the development of a hybrid CPU/GPU architecture and the utilization of modern GPU libraries to accelerate critical operations. Keywords: quantum computing, quantum simulation, Qiskit Aer, MPS, statevector, cudaq.
Today's quantum processors have tens to hundreds of physical qubits, but reliable execution of arbitrary circuits remains limited to fewer than 30 entangled qubits across hardware modalities. Building upon prior work, we introduce an error- and topology-aware method for mapping multiple independent circuits onto disjoint regions of a single large-scale QPU for parallel circuit execution. For applications with many similarly sized circuits, such as observable estimation for Hamiltonian simulation, this approach can reduce billed QPU execution time, with ideal speedup proportional to the number of usable partitions. We demonstrate the approach on IBM's 156-qubit ibm_boston processor using standard QED-C benchmark and Hamiltonian-based observable-estimation workloads. Compared with standard sequential execution, parallel execution reduces billed execution time by 3.5-5.5x while retaining 83-92% of the sequential fidelity. We further evaluate the scaling of parallel circuit execution using GPU-accelerated classical simulation, distributing measurement circuits across GPUs via MPI. Using CUDA-Q on the NERSC Perlmutter system, we achieve up to 13.8x speedup on 16 GPUs (86% parallel efficiency) for an H2 electronic-structure simulation, with scaling evaluated across multiple Hamiltonians and circuit counts. These results provide an indication of the performance ceiling that parallel execution on future quantum hardware may eventually approach. Both execution modes are implemented as a runtime option within the QED-C Application-Oriented Benchmark suite. Together, the results show that circuit-level parallelism can reduce execution cost on current quantum hardware and simulation time on GPU clusters, with the potential for greater benefits as device quality and qubit counts increase.