Quantum error correction suppresses noise in quantum systems to allow for high-precision computations. In this Letter, we introduce multivariate bicycle quantum low-density parity-check (QLDPC) codes, via an extension of the framework developed by Bravyi [S. Bravyi, A. W. Cross, J. M. Gambetta, D. Maslov, P. Rall, and T. J. Yoder, ], and particularly focus on trivariate bicycle (TB) codes. Unlike the weight-6 codes proposed in their study, we offer concrete examples of weight-5 TB-QLDPC codes which promise to be more amenable to near-term experimental setups. We show that TB-QLDPC codes up to weight 6 have a biplanar structure and often possess a two-dimensional toric layout. Under circuit level noise, we find substantially better encoding rates than comparable surface codes while offering similar error suppression capabilities. For example, we can encode four logical qubits with distance 5 into 60 physical qubits using weight-5 check measurements of circuit depth 7, while a surface code with these parameters requires 200 physical qubits. The high encoding rate and compact layout make our codes highly suitable candidates for near-term hardware implementations, paving the way for a realizable quantum error correction protocol.
Quantum error correction suppresses noise in quantum systems to allow for high-precision computations. In this Letter, we introduce multivariate bicycle quantum low-density parity-check (QLDPC) codes, via an extension of the framework developed by Bravyi [S. Bravyi, A. W. Cross, J. M. Gambetta, D. Maslov, P. Rall, and T. J. Yoder, ], and particularly focus on trivariate bicycle (TB) codes. Unlike the weight-6 codes proposed in their study, we offer concrete examples of weight-5 TB-QLDPC codes which promise to be more amenable to near-term experimental setups. We show that TB-QLDPC codes up to weight 6 have a biplanar structure and often possess a two-dimensional toric layout. Under circuit level noise, we find substantially better encoding rates than comparable surface codes while offering similar error suppression capabilities. For example, we can encode four logical qubits with distance 5 into 60 physical qubits using weight-5 check measurements of circuit depth 7, while a surface code with these parameters requires 200 physical qubits. The high encoding rate and compact layout make our codes highly suitable candidates for near-term hardware implementations, paving the way for a realizable quantum error correction protocol.
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.
High-rate quantum low-density parity-check (qLDPC) codes can substantially reduce qubit overhead relative to surface codes, but their advantage depends on efficiently realizing nonlocal syndrome extraction. We study the [[144,12,12]] bivariate bicycle code on a neutral-atom architecture with native three-dimensional (3D) geometry, comparing planar and 3D embeddings while holding the code fixed. We characterize spatial efficiency using the logical-qubit density, defined as the number of encoded logical qubits per unit spatial footprint. Because the optical controller's field of view limits the transverse extent of an array, this metric estimates the number of logical qubits that can be accommodated within a fixed optical field of view. The 3D embedding achieves approximately 4× greater areal logical-qubit density than the planar layout and 42× greater than a surface-code baseline. It also reduces the bivariate bicycle syndrome-extraction time by roughly 2× compared to a planar baseline, with fewer movement operations and substantially shorter atom-transport distance. Native 3D geometry can improve both the packing density and executable realization of nonlocal qLDPC codes, making practical performance depend jointly on code structure, optical geometry, transport scheduling, and hardware-level noise. This motivates further development of control techniques in 3D.
Quantum low-density parity-check (qLDPC) codes are promising candidates for fault-tolerant quantum computation due to their high encoding rates and distances. However, implementing logical operations using qLDPC codes presents significant challenges. Previous research has demonstrated that self-dual qLDPC codes facilitate the implementation of transversal Clifford gates. Here we introduce a method for constructing self-dual qLDPC codes by stacking non-self-dual qLDPC codes. Leveraging this methodology, we develop double-chain bicycle codes, double-layer bivariate bicycle (BB) codes, double-layer twisted BB codes, and double-layer reflection codes, many of which exhibit favorable code parameters. Additionally, we conduct numerical calculations to assess the performance of these codes as quantum memory under the circuit-level noise model, revealing that the logical failure rate can be significantly reduced with high pseudo-thresholds.
Although high-threshold and low-overhead quantum low-density parity-check (qLDPC) codes, such as bivariate bicycle (BB) codes, can reduce the physical-qubit cost by an order of magnitude compared to the Kitaev toric code, their torus layout remains difficult for physical implementation. In this work, we introduce the first systematic procedure to convert BB codes into fully planar, open-boundary qLDPC codes, preserving their performance. We present planar code families with logical dimensions 6 ≤ k ≤ 13 , e.g., ⟦ 78 , 6 , 6 ⟧ , ⟦ 107 , 7 , 7 ⟧ , ⟦ 268 , 8 , 12 ⟧ , ⟦ 405 , 9 , 15 ⟧ , ⟦ 348 , 10 , 13 ⟧ , ⟦ 450 , 11 , 15 ⟧ , ⟦ 386 , 12 , 12 ⟧ , and ⟦ 362 , 13 , 11 ⟧ , all with geometrically local weight-6 stabilizers. Allowing weight-8 stabilizers produces a ⟦ 282 , 12 , 14 ⟧ code, exhibiting an efficiency metric ( k d 2 / n ) an order of magnitude higher than the surface code. The construction combines boundary-anyon condensation with the “lattice-grafting” optimization, yielding high-performance qLDPC codes natively compatible with planar hardware architectures. It also uncovers Sierpinski-type fractal logical operators the distance of which scales with the fractal area on finite lattices. These planar qLDPC codes provide an implementable route to resource-efficient, high-threshold fault tolerance and a flexible framework for future code design on realistic two-dimensional hardware.
Suppressing errors is the central challenge for useful large-scale quantum computing. While quantum error correction promises a viable solution to this challenge, existing codes typically suffer from trade-offs among encoding efficiency, error threshold, and hardware feasibility. Here, we introduce Cornucopia codes, a family of practical, hardware-efficient quantum low-density parity-check codes that achieve an ultra-high encoding rate exceeding 1/2 while maintaining a pseudo-threshold exceeding 0.4% under the standard circuit-level noise model. Inspired by recent affine-permutation-based code constructions and the long-range connectivity available in reconfigurable neutral-atom arrays, we adopt a structured code geometry in which the code layout, atom rearrangement, and syndrome-extraction schedule are co-designed. This structure enables nonlocal syndrome measurements through simple, parallel atom rearrangements. A complete syndrome extraction cycle measures all X- and Z-type checks in parallel with 12 entangling layers, independent of the code size. The resulting threshold is comparable to those of the surface code and bivariate bicycle codes. In particular, a single code block [[2844,1426,18]] encodes 1,426 distance-18 logical qubits, achieving an extrapolated logical error rate of 2.6×10−16 (1.9×10−31) per logical qubit per cycle, assuming the physical error rate of 0.1% (0.01%). By comparison, a bivariate bicycle code implementation would require more than 68,000 physical qubits to encode the same number of logical qubits at a comparable logical error rate. These results bring demonstrations of ultra-low-overhead quantum error correction within the reach of near-term quantum processors.
Quantum computers are predicted to be able to solve problems impossible for a classical supercomputer. The quantum computers that we have now are however very sensitive to noise from their environment, which makes their results unreliable. This necessitates quantum error correction, the main topic of this thesis. Specifically, this thesis concerns quantum Low Density Parity Check (qLDPC) codes for superconducting qubits. Superconducting qubits are one of the ways to implement a quantum computer, used for example by Google and IBM. qLDPC codes are error-correcting codes whose classical counterpart is used in 5G and Wi-Fi, among other applications. They are a type of stabilizer code, meaning that the quantum state we wish to store is subjected to a sequence of non-destructive measurements, whose results can tell if an error has occurred or not. Explaining this more in-depth is the bulk of this thesis. The qLDPC code chosen as most fitting for superconducting qubits is the bivariate bicycle (BB) code. In it, each qubit interacts with its four nearest neighbours as well as with two qubits further away, which allows for fewer qubits to be needed for the same error-correcting performance. The results were collected in the following order: First, different decoders (classical algorithms that determine the most likely error based on the results of the non-destructive measurements mentioned above) are compared to determine which performs best. That turned out to be relay Belief Propagation (BP-relay), which is a version of standard BP that uses information from failed decoding rounds to initialize new rounds. BP-relay is then used to compare BB codes with the surface code, another error-correcting code, with the result that the BB code outperforms the surface code. In addition, the feasibility of implementing BB codes on current hardware is explored, with the error rates of IBM's latest chip showing promising performance, even for much worse non-local connections. This implies that qLDPC codes could be used in the near term to increase the fault tolerance of current quantum computers.