Quantum computers are predicted to be able to solve problems impossible for a classical supercomputer. The quantum computers that we have now are however very sensitive to noise from their environment, which makes their results unreliable. This necessitates quantum error correction, the main topic of this thesis. Specifically, this thesis concerns quantum Low Density Parity Check (qLDPC) codes for superconducting qubits. Superconducting qubits are one of the ways to implement a quantum computer, used for example by Google and IBM. qLDPC codes are error-correcting codes whose classical counterpart is used in 5G and Wi-Fi, among other applications. They are a type of stabilizer code, meaning that the quantum state we wish to store is subjected to a sequence of non-destructive measurements, whose results can tell if an error has occurred or not. Explaining this more in-depth is the bulk of this thesis. The qLDPC code chosen as most fitting for superconducting qubits is the bivariate bicycle (BB) code. In it, each qubit interacts with its four nearest neighbours as well as with two qubits further away, which allows for fewer qubits to be needed for the same error-correcting performance. The results were collected in the following order: First, different decoders (classical algorithms that determine the most likely error based on the results of the non-destructive measurements mentioned above) are compared to determine which performs best. That turned out to be relay Belief Propagation (BP-relay), which is a version of standard BP that uses information from failed decoding rounds to initialize new rounds. BP-relay is then used to compare BB codes with the surface code, another error-correcting code, with the result that the BB code outperforms the surface code. In addition, the feasibility of implementing BB codes on current hardware is explored, with the error rates of IBM's latest chip showing promising performance, even for much worse non-local connections. This implies that qLDPC codes could be used in the near term to increase the fault tolerance of current quantum computers.
Quantum computers are predicted to be able to solve problems impossible for a classical supercomputer. The quantum computers that we have now are however very sensitive to noise from their environment, which makes their results unreliable. This necessitates quantum error correction, the main topic of this thesis. Specifically, this thesis concerns quantum Low Density Parity Check (qLDPC) codes for superconducting qubits. Superconducting qubits are one of the ways to implement a quantum computer, used for example by Google and IBM. qLDPC codes are error-correcting codes whose classical counterpart is used in 5G and Wi-Fi, among other applications. They are a type of stabilizer code, meaning that the quantum state we wish to store is subjected to a sequence of non-destructive measurements, whose results can tell if an error has occurred or not. Explaining this more in-depth is the bulk of this thesis. The qLDPC code chosen as most fitting for superconducting qubits is the bivariate bicycle (BB) code. In it, each qubit interacts with its four nearest neighbours as well as with two qubits further away, which allows for fewer qubits to be needed for the same error-correcting performance. The results were collected in the following order: First, different decoders (classical algorithms that determine the most likely error based on the results of the non-destructive measurements mentioned above) are compared to determine which performs best. That turned out to be relay Belief Propagation (BP-relay), which is a version of standard BP that uses information from failed decoding rounds to initialize new rounds. BP-relay is then used to compare BB codes with the surface code, another error-correcting code, with the result that the BB code outperforms the surface code. In addition, the feasibility of implementing BB codes on current hardware is explored, with the error rates of IBM's latest chip showing promising performance, even for much worse non-local connections. This implies that qLDPC codes could be used in the near term to increase the fault tolerance of current quantum computers.
Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.
Quantum low-density parity-check (qLDPC) codes are promising candidates for fault-tolerant quantum computation due to their high encoding rates and distances. However, implementing logical operations using qLDPC codes presents significant challenges. Previous research has demonstrated that self-dual qLDPC codes facilitate the implementation of transversal Clifford gates. Here we introduce a method for constructing self-dual qLDPC codes by stacking non-self-dual qLDPC codes. Leveraging this methodology, we develop double-chain bicycle codes, double-layer bivariate bicycle (BB) codes, double-layer twisted BB codes, and double-layer reflection codes, many of which exhibit favorable code parameters. Additionally, we conduct numerical calculations to assess the performance of these codes as quantum memory under the circuit-level noise model, revealing that the logical failure rate can be significantly reduced with high pseudo-thresholds.
Quantum low-density parity-check (QLDPC) codes with good parameters are promising candidates for low-overhead fault-tolerant quantum computing, but their non-local stabilizers require long-range connectivity and frequent qubit movement, introducing practical challenges. Prior work has studied the networked implementation of topological codes, where each node only holds one or a few qubits of the entire code, and demonstrated competitive performance under practical constraints such as the quality of network-provided entanglement. However, since these codes are already geometrically local, such a networked setting might not be essential. In this work, we propose and study the networked implementation of better QLDPC codes, specifically bivariate bicycle codes due to their similarity to surface codes and the controlled amount of long-range connections in their stabilizers. We begin by recreating networked surface codes in Stim, with one code qubit per node, and provide additional insights into their circuit-level noise performance. We then extend this approach to bipartitions of bivariate bicycle codes, using balanced min-cut partitioning on their combined X-Z Tanner graph to identify optimal qubit splits. For stabilizers spanning nodes, we implement teleported CNOTs and vary the Bell pair fidelity enabling these gates. Through circuit-level noise simulations with BP-OSD decoding, we provide the first insights into networked realizations of these codes and compare their performance with monolithic implementations. We conclude by outlining advantages, limitations, and future directions.
Utility-scale quantum computing requires quantum error correction (QEC) to protect quantum information against noise. Currently, superconducting hardware is a promising candidate for achieving fault tolerance due to its fast gate times and feasible scalability. However, it is often restricted to two-dimensional nearest-neighbour connectivity, and therefore the variety of quantum low-density parity-check (qLDPC) codes that can be implemented on it without sacrificing QEC performance is believed to be greatly restricted. In this paper we construct a new family of qLDPC codes, which we call ``directional codes'', that outperforms the rotated toric code (RTC) while satisfying the connectivity requirements of the widely adopted square-grid, and some even the sparser hexagonal-grid, on a torus. The key idea is to utilise the iSWAP gate -- a native gate demonstrated on superconducting qubits -- to construct circuits that measure the stabilisers of these qLDPC codes without the need for additional connections. We numerically evaluate the performance of directional codes, encoding four, six, twelve and eighteen logical qubits, using a common superconducting-inspired circuit-level Pauli noise model. We also compare them to the RTC and to the bivariate bicycle (BB) codes, currently the two most popular quantum LDPC code families. As a concrete example, when evaluated with the Tesseract decoder with short beam setting, the best directional code family investigated achieves the same logical error rate as the RTC at physical error rate p=10−3 but requires only a quarter to a third of the number of physical qubits. Our discovery opens a novel direction in QEC code design, suggesting that complex high-connectivity hardware may not be necessary for low-overhead fault-tolerant quantum computation.
The major challenge on the way to fault-tolerant quantum computing comes from the insufficient quality of hardware components and the difficulty of scaling their number without further compromising fidelity. Quantum Low-Density Parity-Check (qLDPC) codes offer a promising solution by encoding logical qubits with low overhead and at a comparatively high code distance. However, it remains an open question how to scalably implement efficient qLDPC codes on fixed-connectivity quantum chips without increasing hardware complexity to enable the non-local interactions in their underlying QEC cycles. We resolve this challenge for the first time by introducing a family of qLDPC "barbell" codes accompanied by a realistic chip layout that natively supports all required two-qubit interactions. Crucially, the hardware complexity required to implement barbell codes remains constant as code distance increases. We provide a detailed investigation into the feasibility of all required hardware components and simulate a specific family of barbell codes against circuit-level noise. We find that, with a modest overhead of <30 data qubits per logical qubit, barbell codes can preserve information at a physical noise strength of 10−4 for several trillion QEC cycles. Simulations of logical multi-Pauli measurements, performed with circuits tailored to the chip, yield similar logical performance per QEC round, indicating that entangling gates between logical qubits in barbell codes can be realized fault-tolerantly.