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arXiv:2504.08887 · PRX Quantum

Planar Quantum Low-Density Parity-Check Codes with Open Boundaries

Zijian Liang, Jens Niklas Eberhardt, Yu-An Chen

Published Nov 12, 2025• 4 citations
arXivHTMLPDF

Abstract

Although high-threshold and low-overhead quantum low-density parity-check (qLDPC) codes, such as bivariate bicycle (BB) codes, can reduce the physical-qubit cost by an order of magnitude compared to the Kitaev toric code, their torus layout remains difficult for physical implementation. In this work, we introduce the first systematic procedure to convert BB codes into fully planar, open-boundary qLDPC codes, preserving their performance. We present planar code families with logical dimensions 6 ≤ k ≤ 13 , e.g., ⟦ 78 , 6 , 6 ⟧ , ⟦ 107 , 7 , 7 ⟧ , ⟦ 268 , 8 , 12 ⟧ , ⟦ 405 , 9 , 15 ⟧ , ⟦ 348 , 10 , 13 ⟧ , ⟦ 450 , 11 , 15 ⟧ , ⟦ 386 , 12 , 12 ⟧ , and ⟦ 362 , 13 , 11 ⟧ , all with geometrically local weight-6 stabilizers. Allowing weight-8 stabilizers produces a ⟦ 282 , 12 , 14 ⟧ code, exhibiting an efficiency metric ( k d 2 / n ) an order of magnitude higher than the surface code. The construction combines boundary-anyon condensation with the “lattice-grafting” optimization, yielding high-performance qLDPC codes natively compatible with planar hardware architectures. It also uncovers Sierpinski-type fractal logical operators the distance of which scales with the fractal area on finite lattices. These planar qLDPC codes provide an implementable route to resource-efficient, high-threshold fault tolerance and a flexible framework for future code design on realistic two-dimensional hardware.

DOI
10.1103/qv65-vmzr

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Although high-threshold and low-overhead quantum low-density parity-check (qLDPC) codes, such as bivariate bicycle (BB) codes, can reduce the physical-qubit cost by an order of magnitude compared to the Kitaev toric code, their torus layout remains difficult for physical implementation. In this work, we introduce the first systematic procedure to convert BB codes into fully planar, open-boundary qLDPC codes, preserving their performance. We present planar code families with logical dimensions 6 ≤ k ≤ 13 , e.g., ⟦ 78 , 6 , 6 ⟧ , ⟦ 107 , 7 , 7 ⟧ , ⟦ 268 , 8 , 12 ⟧ , ⟦ 405 , 9 , 15 ⟧ , ⟦ 348 , 10 , 13 ⟧ , ⟦ 450 , 11 , 15 ⟧ , ⟦ 386 , 12 , 12 ⟧ , and ⟦ 362 , 13 , 11 ⟧ , all with geometrically local weight-6 stabilizers. Allowing weight-8 stabilizers produces a ⟦ 282 , 12 , 14 ⟧ code, exhibiting an efficiency metric ( k d 2 / n ) an order of magnitude higher than the surface code. The construction combines boundary-anyon condensation with the “lattice-grafting” optimization, yielding high-performance qLDPC codes natively compatible with planar hardware architectures. It also uncovers Sierpinski-type fractal logical operators the distance of which scales with the fractal area on finite lattices. These planar qLDPC codes provide an implementable route to resource-efficient, high-threshold fault tolerance and a flexible framework for future code design on realistic two-dimensional hardware.
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Quantum low-density parity-check (qLDPC) codes are promising candidates for fault-tolerant quantum computation due to their high encoding rates and distances. However, implementing logical operations using qLDPC codes presents significant challenges. Previous research has demonstrated that self-dual qLDPC codes facilitate the implementation of transversal Clifford gates. Here we introduce a method for constructing self-dual qLDPC codes by stacking non-self-dual qLDPC codes. Leveraging this methodology, we develop double-chain bicycle codes, double-layer bivariate bicycle (BB) codes, double-layer twisted BB codes, and double-layer reflection codes, many of which exhibit favorable code parameters. Additionally, we conduct numerical calculations to assess the performance of these codes as quantum memory under the circuit-level noise model, revealing that the logical failure rate can be significantly reduced with high pseudo-thresholds.
Abstract Fault-tolerant quantum computation critically depends on architectures uniting high encoding rates with physical implementability. Quantum low-density parity-check (qLDPC) codes, including bivariate bicycle (BB) codes, achieve dramatic reductions in qubit overhead, yet their logical operations remain a key challenge under planar hardware constraints. Here, we introduce code craft, a framework for designing fault-tolerant logical operations on planar BB codes within a translationally invariant, two-dimensional qubit lattice. By systematically deforming codes through local modifications---stretching, cutting, and painting---we enable the manipulation of logical qubits using strictly planar operations. We establish fault tolerance through numerical optimization of code distances and show that logical operations, including controlled-NOT gates, state transfers, and Pauli measurements, can be efficiently implemented within this framework to assemble an individually addressable logical qubit network. Universal quantum computation can then be realized by coupling just one BB-code logical qubit to a surface-code block. By combining the high encoding efficiency of qLDPC codes with geometric locality, our approach offers a practical and resource-efficient path to fault-tolerant quantum computation.
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are competitive to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism translates into quantifiable benefits, substantially reducing wiring crossings in superconducting multi-layer architectures and simplifying the scheduling of atom movement in neutral-atom arrays. The weight-7 routing codes maintain a high threshold of 0.7\% and reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. Further increasing the weight to 11 yields a [[200, 24, 14]] and [[200, 16, 17]] codes with an encoding rate over 23 times that of the surface code, at the cost of a higher logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.
High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.
Quantum low-density parity-check (qLDPC) codes offer a promising route to scalable fault-tolerant quantum computation with constant overhead. Recent advancements have shown that qLDPC codes can outperform the quantum memory capability of surface codes even with near-term hardware. The question of how to implement logical gates fault-tolerantly for these codes is still open. We present new examples of high-rate bivariate bicycle (BB) codes with enhanced symmetry properties. These codes feature explicit nice bases of logical operators (similar to toric codes) and support fold-transversal Clifford gates. As examples, we construct[[98,6,12]][[{98,6,12}]][[98,6,12]]and[[162,8,12]][[{162, 8, 12}]][[162,8,12]]BB codes which admit interesting fault-tolerant Clifford gates. Our work also lays the mathematical foundations for explicit bases of logical operators and fold-transversal gates in quantum two-block group algebra codes, which might be of independent interest.