Current quantum computing platforms suffer from readout errors, where faulty measurement outcomes are reported by the device. These errors are particularly harmful in quantum programs that rely on branch statements, where operations in later parts of the program are dynamically determined by mid-circuit measurements. We propose a general protocol for mitigating mid-circuit measurement errors. Our solution works for any number of mid-circuit measurement and feedforward layers without increasing circuit depth or two-qubit gate counts, is efficient under structural assumptions on error channels, and is suitable for immediate application on noisy intermediate-scale quantum devices. We experimentally demonstrate up to a ∼ 60 % reduction in error on superconducting quantum processors across several practically relevant feedforward circuits, including dynamic qubit resets, shallow-depth Greenberger–Horne–Zeilinger state preparation, and multistage quantum teleportation. This work paves the way for more error-resilient adaptive quantum circuits, crucial for current and future quantum computing applications.
Current quantum computing platforms suffer from readout errors, where faulty measurement outcomes are reported by the device. These errors are particularly harmful in quantum programs that rely on branch statements, where operations in later parts of the program are dynamically determined by mid-circuit measurements. We propose a general protocol for mitigating mid-circuit measurement errors. Our solution works for any number of mid-circuit measurement and feedforward layers without increasing circuit depth or two-qubit gate counts, is efficient under structural assumptions on error channels, and is suitable for immediate application on noisy intermediate-scale quantum devices. We experimentally demonstrate up to a ∼ 60 % reduction in error on superconducting quantum processors across several practically relevant feedforward circuits, including dynamic qubit resets, shallow-depth Greenberger–Horne–Zeilinger state preparation, and multistage quantum teleportation. This work paves the way for more error-resilient adaptive quantum circuits, crucial for current and future quantum computing applications.
Quantum error mitigation (QEM) for dynamic circuits, i.e., those incorporating mid-circuit measurements and feedforward, is important for two key reasons. First, quantum error correction (QEC) circuits are instances of dynamic circuits, and therefore a dynamic circuit-compatible QEM can extend circuit depth and address errors that QEC struggles with. Second, recent studies show that dynamic circuits can significantly outperform purely unitary ones. However, mid-circuit measurement errors remain a major bottleneck. Current solutions rely on readout noise characterization that is vulnerable to temporal noise drifts. To the best of our knowledge, no readout mitigation schemes are resilient to temporal noise drifts. By introducing parity-based noise amplification in repeated measurements, we derive and experimentally demonstrate a drift-resilient protocol for addressing preparation, mid-circuit, and terminating measurement errors without requiring calibration or characterization. Drift resilience increases the longest possible execution time (in terms of shots) and enables flexibility by combining data from non-consecutive times. For platforms such as trapped ions, where the measurements are highly disruptive, we provide an alternative reset-based mitigation scheme. We demonstrate our methods experimentally on IBMQ and Quantinuum hardware. Combined with the Layered-KIK gate error mitigation protocol, the presented readout mitigation approach enables "End-to-end" mitigation for dynamic circuits, that can improve the outcomes of QEC experiments, and that covers the widest range of errors to the best of our knowledge. Other applications of the presented methods include a faster alternative to gate-set tomography and diagnostics of defective qubits during the execution of the target algorithm.
Mid-circuit measurement and classical feed-forward are essential primitives for dynamic-circuit teleportation on superconducting quantum processors. However, the error associated with measurement-conditioned corrective operations remains poorly understood when evaluated with respect to individual measurement branches. In this paper, we present a framework for characterizing feed-forward error in dynamic circuit teleportation without losing valuable information related to its behavior across separate branches. We analyze three approaches to applying measurement-conditioned corrections: (i) physical application, (ii) post-processing adjustments, and (iii) a mitigated physical application which utilizes Bit-Flip Averaging (BFA)-based Probabilistic Readout Error Mitigation (PROM). We experimentally reconstruct branch Choi operators via an entangled reference qubit, and validate our physical-application and post-processing Choi-shadow estimators against full tomography of the branch Choi operators. We perform experiments on two physical qubit layouts which differ greatly in mid-circuit measurement readout error, and observe a reversal in the relative order in branch qualities obtained from the post-processing and PROM mitigation strategies. In one physical layout with higher measurement readout error, the operational feed-forward penalty is relatively modest (approximately 0.02-0.03) and PROM produces higher branch qualities than post-processing for every branch. In a separate layout with lower readout error, the operational feed-forward penalty increases to roughly 0.07, and post-processing exceeds PROM for all branch qualities. Our characterization framework can reveal branch-specific error structure and mitigation behavior that state-of-the-art outcome-averaged analyses fail to expose.
Dynamic quantum circuits integrate mid-circuit measurements and feed-forward operations to enable real-time classical processing and conditional quantum logic. These capabilities are central to key quantum protocols such as quantum error correction, and have recently demonstrated significant potential for reducing quantum resources, including circuit depth and gate count, across a range of applications. However, executing dynamic circuits on real quantum hardware introduces a critical trade-off: while resource requirements decrease, circuit fidelity degrades due to high error rates of mid-circuit measurements, as well as the decoherence errors accumulated during the extended idle periods introduced by both mid-circuit measurements and feed-forward operations. In this paper, we systematically investigate the impact of standard error mitigation techniques on dynamic circuit applications pertaining to Hamiltonian simulation and ground state estimation of physically relevant systems like the Heisenberg model. We explore dynamical decoupling (DD) as a strategy to suppress decoherence and crosstalk errors during idle windows introduced by mid-circuit measurements and feed-forward delays, and also examine error mitigation via zero-noise extrapolation (ZNE). Through experiments conducted on IBM quantum hardware, we benchmark effective combinations of these strategies that maximize the practical benefits of dynamic quantum circuits in these applications. We demonstrate that a combination of DD and ZNE is effective in mitigating the errors introduced during mid-circuit measurements and feed-forward operations, as well as the errors arising from faulty measurements. This approach yields a energy gap improvement of at least 60% in ground state estimation and reduces observed error of time-evolved states by up to 99% for the Ising model and up to 20% for the Heisenberg model.
Current noisy quantum computers have multiple types of errors, which can occur in the state preparation, measurement/readout, and gate operation, as well as intrinsic decoherence and relaxation. Partly motivated by the booming of intermediate-scale quantum processors, measurement and gate errors have been recently extensively studied, and several methods of mitigating them have been proposed and formulated in software packages (e.g., in IBM Qiskit). Despite this, the state preparation error and the procedure to quantify it have not yet been standardized, as state preparation and measurement errors are usually considered not directly separable. Inspired by a recent work of Laflamme, Lin, and Mor \cite{laflamme2022algorithmic}, we propose a simple and resource-efficient approach to quantify separately the state preparation and readout error rates. With these two errors separately quantified, we also propose methods to mitigate them separately, especially mitigating state preparation errors with linear (with the number of qubits) complexity. As a result of the separate mitigation, we show that the fidelity of the outcome can be improved by an order of magnitude compared to the standard measurement error mitigation scheme. We also show that the quantification and mitigation scheme is resilient against gate noise and can be immediately applied to current noisy quantum computers. To demonstrate this, we present results from cloud experiments on IBM's superconducting quantum computers. The results indicate that the state preparation error rate is also an important metric for qubit metrology that can be efficiently obtained.
Distributed Quantum Computing (DQC) and Quantum Error Correction (QEC) rely on dynamic circuits that include Mid-Circuit Measurements (MCMs) and classical feedback. These operations present a major bottleneck: MCMs suffer from high error rates that lead to real-time branching errors, while MCM and classical feedback latencies amplify decoherence errors. Current hardware controllers, qubit-state discriminators, and software error mitigation techniques fail to address these challenges holistically.
We propose MCMit, a hardware-software co-design to mitigate branching and latency-induced errors. MCMit introduces a scalable, constant-latency multi-control branch instruction for faster classical feedback and two qubit-state discriminators, a transformer, and a CNN, with high accuracy even under short measurement durations. On the software side, static MCM elimination and stochastic branching complement the hardware by mitigating residual branching errors that persist despite hardware improvements.
We implement MCMit on Qubic and evaluate it using experimentally extracted QPU readout traces. Our branch instruction reduces feedback latency by up to 70\%, improving circuit depths by up to 7× over Qubic. Our CNN discriminator achieves up to 62\% higher accuracy for short measurement durations than the baselines, driving 1.2−9.4× lower logical error rates in QEC. Last, our software mitigation improves fidelity by 18--30\% over baseline methods in DQC workloads.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.