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arXiv:2404.18038 · IEEE International Conference on Quantum Computing and Engineering (QCE)

Multi-Stage Watermarking for Quantum Circuits

Yang Min, Xiaolong Guo, Lei Jiang

Published Sep 15, 2024• 9 citations
arXivHTMLPDF

Abstract

Quantum computing represents a burgeoning computational paradigm that significantly advances the resolution of contemporary intricate problems across various domains, including cryptography, chemistry, and machine learning. Quantum circuits tailored to address specific problems have emerged as critical intellectual properties (IPs) for quantum computing companies, attributing to the escalating commercial value of quantum computing. Consequently, designing watermarking schemes for quantum circuits becomes imperative to thwart malicious entities from producing unauthorized circuit replicas and unlawfully disseminating them within the market. Unfortunately, the prevailing watermarking technique reliant on unitary matrix decomposition markedly inflates the number of 2-qubit gates and circuit depth, thereby compromising the fidelity of watermarked circuits when embedding detectable signatures into the corresponding unitary matrices. In this paper, we propose an innovative multi-stage watermarking scheme for quantum circuits, introducing additional constraints across various synthesis stages to validate the ownership of IPs. Compared to the state-of-the-art watermarking technique, our multi-stage watermarking approach demonstrates, on average, a reduction in the number of 2-qubit gates by 16% and circuit depth by 6%, alongside an increase in the fidelity of watermarked circuits by 8%, while achieving a 79.4% lower probabilistic proof of authorship.

DOI
10.1109/qce60285.2024.00099

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Quantum computing represents a burgeoning computational paradigm that significantly advances the resolution of contemporary intricate problems across various domains, including cryptography, chemistry, and machine learning. Quantum circuits tailored to address specific problems have emerged as critical intellectual properties (IPs) for quantum computing companies, attributing to the escalating commercial value of quantum computing. Consequently, designing watermarking schemes for quantum circuits becomes imperative to thwart malicious entities from producing unauthorized circuit replicas and unlawfully disseminating them within the market. Unfortunately, the prevailing watermarking technique reliant on unitary matrix decomposition markedly inflates the number of 2-qubit gates and circuit depth, thereby compromising the fidelity of watermarked circuits when embedding detectable signatures into the corresponding unitary matrices. In this paper, we propose an innovative multi-stage watermarking scheme for quantum circuits, introducing additional constraints across various synthesis stages to validate the ownership of IPs. Compared to the state-of-the-art watermarking technique, our multi-stage watermarking approach demonstrates, on average, a reduction in the number of 2-qubit gates by 16% and circuit depth by 6%, alongside an increase in the fidelity of watermarked circuits by 8%, while achieving a 79.4% lower probabilistic proof of authorship.
Quantum circuits constitute Intellectual Property (IP) of the quantum developers and users, which needs to be protected from theft by adversarial agents e.g., the quantum cloud provider or a rogue adversary present in the cloud. This necessitates the exploration of low-overhead techniques applicable to near-term quantum devices, to trace the quantum circuits/algorithms' IP and their output. We present two such lightweight watermarking techniques to prove ownership in the event of an adversary cloning the circuit design. For the first technique a rotation gate is placed on ancilla qubits combined with other gate (s) at the output of the circuit. For the second method, a set of random gates are inserted in the middle of the circuit followed by its inverse, separated from the circuit by a barrier. These models are combined and applied on benchmark circuits and the circuit depth, 2-qubit gate count, probability of successful trials (PST) and probabilistic proof of authorship (PPA) are compared against the state-of-the-art. The PST is reduced by a miniscule 0.53% against the non-watermarked benchmarks and is up to 22.69% higher compared to existing techniques. The circuit depth has been reduced by up to 27.7% as against the state-of-the-art. The PPA is astronomically smaller than existing watermarks.
Quantum computing is an emerging computing paradigm that is expected to offer decisive advantages for critical applications. The design flow of quantum circuits poses problematic security challenges in the presence of variable errors and limited resources (qubits) to support error correction. Yet, quantum computers can be very powerful for several applications if proper hardware/software approaches are deployed.In the current embodiment, quantum circuits are expected to be used for several applications including financial analysis and machine learning in which a designer wants to protect the Intellectual Property (IP) of the quantum circuits. In this paper, we propose a watermarking approach for quantum circuits, which embeds a secret signature during the decomposition phase to verify the ownership of the IP. We evaluate the effectiveness of the proposed approach using Quantum Approximate optimization Algorithm (QAOA) used for solving a Max-Cut problem.
We introduce a barrier-free watermarking framework for quantum circuits that embeds authorship as a controlled measurement bias on dedicated ancilla qubits while preserving the functional behavior of the original computation when the ancillas are ignored. Each watermark block prepares an ancilla and couples it once to a selected work qubit using an interaction that preserves the ancilla's measurement statistics, and blocks are placed before measurement to avoid compiler reordering across readout. Because the watermark is defined by a statistical property rather than a specific gate pattern, it is designed to remain verifiable after standard transpilation and hardware mapping. We provide a Qiskit implementation and an evaluation protocol that measures watermark detectability, functional impact on the circuit output distribution, and performance overhead. Experiments on RevLib benchmarks, simulator backends, and IBM quantum hardware show that the watermark can be detected reliably while introducing only modest degradation under typical NISQ noise levels, with the tradeoff becoming more pronounced as circuit depth increases.
Abstract This paper presents a spatial domain quantum watermarking scheme. For a quantum watermarking scheme, a feasible quantum circuit is a key to achieve it. This paper gives a feasible quantum circuit for the presented scheme. In order to give the quantum circuit, a new quantum multi-control rotation gate, which can be achieved with quantum basic gates, is designed. With this quantum circuit, our scheme can arbitrarily control the embedding position of watermark images on carrier images with the aid of auxiliary qubits. Besides reversely acting the given quantum circuit, the paper gives another watermark extracting algorithm based on quantum measurements. Moreover, this paper also gives a new quantum image scrambling method and its quantum circuit. Differ from other quantum watermarking schemes, all given quantum circuits can be implemented with basic quantum gates. Moreover, the scheme is a spatial domain watermarking scheme, and is not based on any transform algorithm on quantum images. Meanwhile, it can make sure the watermark be secure even though the watermark has been found. With the given quantum circuit, this paper implements simulation experiments for the presented scheme. The experimental result shows that the scheme does well in the visual quality and the embedding capacity.
This paper presents a spatial domain quantum watermarking scheme. For a quantum watermarking scheme,a feasible quantum circuit is a key to achieve it. This paper gives a feasible quantum circuit for the presented scheme. In order to give the quantum circuit, a new quantum multi-control rotation gate, which can be achieved with quantum basic gates, is designed. With this quantum circuit, our scheme can arbitrarily control the embedding position of watermark images on carrier images with the aid of auxiliary qubits. Besides reversely acting the given quantum circuit, the paper gives another watermark extracting algorithm based on quantum measurements. Moreover, this paper also gives a new quantum image scrambling method and its quantum circuit. Differ from other quantum watermarking schemes, all given quantum circuits can be implemented with basic quantum gates. Moreover, the scheme is a spatial domain watermarking scheme, and is not based on any transform algorithm on quantum images. Meanwhile, it can make sure the watermark be secure even though the watermark has been found. With the given quantum circuit, this paper implements simulation experiments for the presented scheme. The experimental result shows that the scheme does well in the visual quality and the embedding capacity.
Quantum computing faces challenges such as noise, short coherence time, and limited qubit connections. These challenges worsen as quantum circuits become more complex. One major issue is the increasing depth of quantum circuits. This research proposes an optimization framework targeting depth and gate count reduction in quantum circuits, specifically for Noisy Intermediate-Scale Quantum (NISQ) devices. The proposed approach combines unitary merging of single-qubit gates, CNOT cancellation, gate commuting, and rotation gate rewriting strategies. Consecutive gates acting on the same qubit, such asRx(θ1)⋅Rx(θ2)R_{x}\left(\theta_{1}\right) \cdot R_{x}\left(\theta_{2}\right)Rx​(θ1​)⋅Rx​(θ2​), are algebraically merged into a single rotation, while pairs of redundant CNOT gates are eliminated based on gate identity relations. The technique is implemented using Qiskit and validated across five diverse circuits including complex, random, and multi-qubit configurations. Experimental results show an average depth reduction of 33.33% and gate count reduction of 32.14%, with runtime improvement of up to 25%. For instance, an input circuit with a depth of 7 and gate count of 11 was reduced to a depth of 2 and 4 gates. All optimized circuits preserve functional correctness with a fidelityF≥0.99F \geq 0.99F≥0.99. High-resolution circuit diagrams are presented to visually demonstrate improvements before and after optimization. Additionally, global phase shifts such aseiπ/4e^{i \pi / 4}eiπ/4are preserved or analytically characterized where relevant. This work enhances the viability of quantum computations on near-term hardware and opens pathways for future AI-driven quantum optimizations.