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arXiv:2403.19809

Arbitrary quantum circuits on a fully integrated two-qubit computation register for a trapped-ion quantum processor

Nicolas Pulido-Mateo, H. Mendpara, Markus Duwe, T. Dubielzig, Giorgio Zarantonello, Ludwig Krinner, C. Ospelkaus

Published Mar 28, 2024• 0 citations
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Abstract

We report on the implementation of arbitrary circuits on a universal two-qubit register that can act as the computational module in a trapped-ion quantum computer based on the quantum charge-coupled device architecture. A universal set of quantum gates is implemented on a two-ion Coulomb crystal of $^9$Be$^+$ ions using only chip-integrated microwave addressing. Individual-ion addressing is implemented using microwave micromotion sideband transitions; we obtain upper limits on addressing cross-talk in the register. Arbitrary two-qubit operations are characterized using the cycle benchmarking protocol.

DOI
10.48550/arxiv.2403.19809

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We report on the implementation of arbitrary circuits on a universal two-qubit register that can act as the computational module in a trapped-ion quantum computer based on the quantum charge-coupled device architecture. A universal set of quantum gates is implemented on a two-ion Coulomb crystal of Be + 9 ions using only chip-integrated microwave addressing. Individual-ion addressing is implemented using microwave micromotion sideband transitions; we obtain upper limits on addressing crosstalk in the register. Arbitrary two-qubit operations are characterized using the cycle benchmarking protocol. Published by the American Physical Society 2024
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=642^6=6426=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Trapped-ion quantum computer hardware is scaling to larger qubit numbers, but the computational capabilities of these devices remain largely unknown. From an abstract computer-science perspective, we address this problem in a two-step approach: First, we categorize levels of qubit connectivity for a processor based on ion-shuttling and individual ion addressing. Second, we apply computer-science techniques to develop optimized compilers that map arbitrary algorithms to sequences of ion-register reconfiguration and gate operations. We present compilers for 1D and 2D architectures, optimizing cost functions such as the qubit reconfiguration effort.
Abstract The trapped-ion quantum charge-coupled device (QCCD) proposal1, 2 lays out a blueprint for a universal quantum computer that uses mobile ions as qubits. Analogous to a charge-coupled device (CCD) camera, which stores and processes imaging information as movable electrical charges in coupled pixels, a QCCD computer stores quantum information in the internal state of electrically charged ions that are transported between different processing zones using dynamic electric fields. The promise of the QCCD architecture is to maintain the low error rates demonstrated in small trapped-ion experiments3–5 by limiting the quantum interactions to multiple small ion crystals, then physically splitting and rearranging the constituent ions of these crystals into new crystals, where further interactions occur. This approach leverages transport timescales that are fast relative to the coherence times of the qubits, the insensitivity of the qubit states of the ion to the electric fields used for transport, and the low crosstalk afforded by spatially separated crystals. However, engineering a machine capable of executing these operations across multiple interaction zones with low error introduces many difficulties, which have slowed progress in scaling this architecture to larger qubit numbers. Here we use a cryogenic surface trap to integrate all necessary elements of the QCCD architecture—a scalable trap design, parallel interaction zones and fast ion transport—into a programmable trapped-ion quantum computer that has a system performance consistent with the low error rates achieved in the individual ion crystals. We apply this approach to realize a teleported CNOT gate using mid-circuit measurement6, negligible crosstalk error and a quantum volume7 of 26 = 64. These results demonstrate that the QCCD architecture provides a viable path towards high-performance quantum computers.
Quantum computers can solve certain problems more efficiently than any possible conventional computer. Small quantum algorithms have been demonstrated on multiple quantum computing platforms, many specifically tailored in hardware to implement a particular algorithm or execute a limited number of computational paths. Here, we demonstrate a five-qubit trapped-ion quantum computer that can be programmed in software to implement arbitrary quantum algorithms by executing any sequence of universal quantum logic gates. We compile algorithms into a fully-connected set of gate operations that are native to the hardware and have a mean fidelity of 98 %. Reconfiguring these gate sequences provides the flexibility to implement a variety of algorithms without altering the hardware. As examples, we implement the Deutsch-Jozsa (DJ) and Bernstein-Vazirani (BV) algorithms with average success rates of 95 % and 90 %, respectively. We also perform a coherent quantum Fourier transform (QFT) on five trappedion qubits for phase estimation and period finding with average fidelities of 62 % and 84 %, respectively. This small quantum computer can be scaled to larger numbers of qubits within a single register, and can be further expanded by connecting several such modules through ion shuttling or photonic quantum channels.
Multilayer surface-electrode ion traps provide a scalable platform for quantum processors. In this paper we present a demonstrator chip designed to implement an 8-qubit shuttling-based quantum processor with chip-integrated microwave control for quantum gates. The design is based on a linear Paul trap geometry. All-to-all connectivity will be implemented through ion swapping. The production of the trap chip is carried out with multistep microfabrication. The 2-layer ion trap chip with two storage registers and an interaction zone has a size of 5 mm x 10 mm . Flexibility in signal routing is improved through the use of thick and planarised metal–dielectric layers. • Fabrication of multilayer asymmetric ion trap chip aiming to enable an 8-qubit quantum computer. • Brief insight into the linear trap chip design with quantum charged-coupled device architecture. • Wafer level multistep microfabrication procedure of the chip production. • Chip characterisation with respect to the target design features and trapping readiness.