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arXiv:2403.19614

Optimizing Josephson Junction Reproducibility in 30 kV E-beam Lithography: Analysis of Backscattered Electron Distribution

Rebello, A. M., L. M. Ruela, Gustavo Moreto, Klein, N. Y., Emiliano Rezende Martins, Ivan S. Oliveira, Francisco P. M. Rouxinol, João Paulo Sinnecker

Published Mar 28, 2024• 0 citations
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Abstract

This paper explores methods to enhance the reproducibility of Josephson junctions, crucial elements in superconducting quantum technologies, when employing the Dolan technique in 30 kV e-beam processes. The study explores the influence of dose distribution along the bridge area on reproducibility, addressing challenges related to fabrication sensitivity. Experimental methods include E-beam lithography, with electron trajectory simulations shedding light on backscattered electron behavior. We demonstrate the fabrication of different junction geometries, revealing that some geometries significantly improve reproducibility by resulting in a more homogeneous dose distribution over the junction area.

DOI
10.48550/arxiv.2403.19614

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This paper explores methods to enhance the reproducibility of Josephson junctions, crucial elements in superconducting quantum technologies, when employing the Dolan technique in 30 kV e-beam processes. The study explores the influence of dose distribution along the bridge area on reproducibility, addressing challenges related to fabrication sensitivity. Experimental methods include E-beam lithography, with electron trajectory simulations shedding light on backscattered electron behavior. We demonstrate the fabrication of different junction geometries, revealing that some geometries significantly improve reproducibility by resulting in a more homogeneous dose distribution over the junction area.
This paper explores methods to enhance the reproducibility of Josephson junctions, which are crucial elements in superconducting quantum technologies, when employing the Dolan technique in 30 kV e-beam processes. The study explores the influence of dose distribution along the bridge area on reproducibility, addressing challenges related to fabrication sensitivity. Experimental methods include e-beam lithography, with electron trajectory simulations shedding light on the behavior of backscattered electrons. Wedescribe the fabrication of various Josephson junction geometries and analyze the correlation between the success rates of different lithography patterns and the simulated distribution of backscattered electrons. Our findings demonstrate a success rate of up to 96.3% for the double-resist 1-step low-energy e-beam lithography process. As a means of implementation strategy, we provide a geometric example that takes advantage of simulated stability regions to administer a controlled, uniform dose across the junction area, introducing novel features to overcome the difficulties associated with fabricating bridge-like structures.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO x based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale Al/AlOx/AlAl/AlO_x/AlAl/AlOx​/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate Al/AlOx/AlAl/AlO_x/AlAl/AlOx​/Al junction fabrication with the critical current variation (σ/Icσ/I_cσ/Ic​) less than 3.9% (from 150×200150\times200150×200 to 150×600150\times600150×600 nm2nm^2nm2 area) and 7.7% (for 100×100100\times100100×100 nm2nm^2nm2 area) over 20×2020\times2020×20 mm2mm^2mm2 chip. Finally, we fabricate separately three 5×105\times105×10 mm2mm^2mm2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubit on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.
Josephson junctions (JJs) are critical components in superconducting quantum circuits, where their electrical properties directly determine qubit transition frequencies. While advances in fabrication have enabled precise control over junction area and oxide thickness, the influence of junction geometry beyond area has remained largely unexplored. Here, we report clear and reproducible evidence that the normal-state resistance (Rn) of JJs depends strongly on geometric parameters, demonstrating that (Rn) exhibits a systematic and reproducible dependence on junction geometry beyond simple area scaling. To account for this behavior, we introduce an edge-resistance model that incorporates perimeter-related contributions to (Rn). Our findings highlight the crucial role of geometric design in JJ electrical characteristics and provide a practical framework for improving frequency precision and uniformity in large-scale superconducting quantum processors.
Superconducting qubits are a promising route to achieving large-scale quantum computers. A key challenge in realising large-scale superconducting quantum processors involves mitigating frequency collisions. In this paper, we present an approach to tuning fixed-frequency qubits with the use of an electron beam to locally anneal the Josephson junction. We demonstrate the ability to both increase and decrease the junction barrier resistance. The technique shows an improvement in wafer scale frequency targetting by assessing the frequency collisions in our qubit architecture. Coherence measurements are also done to evaluate the performance before and after tuning. The tuning process utilises a standard electron beam lithography system, ensuring reproducibility and implementation by any group capable of fabricating these Josephson junctions. This technique has the potential to significantly improve the performance of large-scale quantum computing systems, thereby paving the way for the future of quantum computing.