Parameterized circuit instantiation is a common technique encountered in the generation of circuits for a large class of hybrid quantum-classical algorithms. Despite being supported by popular quantum compilation infrastructures such as IBM Qiskit and Google Cirq, instantiation has not been extensively considered in the context of circuit compilation and optimization pipelines. In this work, we describe algorithms to apply instantiation during two common compilation steps: circuit optimization and gate-set transpilation. When placed in a compilation workflow, our circuit optimization algorithm produces circuits with an average of 13% fewer gates than other optimizing compilers. Our gate-set transpilation algorithm can target any gate-set, even sets with multiple two-qubit gates, and produces circuits with an average of 12% fewer two-qubit gates than other compilers. Overall, we show how instantiation can be incorporated into a compiler workflow to improve circuit quality and enhance portability, all while maintaining a reasonably low compile time overhead.
Parameterized circuit instantiation is a common technique encountered in the generation of circuits for a large class of hybrid quantum-classical algorithms. Despite being supported by popular quantum compilation infrastructures such as IBM Qiskit and Google Cirq, instantiation has not been extensively considered in the context of circuit compilation and optimization pipelines. In this work, we describe algorithms to apply instantiation during two common compilation steps: circuit optimization and gate-set transpilation. When placed in a compilation workflow, our circuit optimization algorithm produces circuits with an average of 13% fewer gates than other optimizing compilers. Our gate-set transpilation algorithm can target any gate-set, even sets with multiple two-qubit gates, and produces circuits with an average of 12% fewer two-qubit gates than other compilers. Overall, we show how instantiation can be incorporated into a compiler workflow to improve circuit quality and enhance portability, all while maintaining a reasonably low compile time overhead.
Quantum software engineering is an emerging research field focusing on efficiently embedding the quantum programming paradigm into existing software ecosystems. A key aspect of this field is the realization of quantum algorithms using gate-based programming and the subsequent low-level optimization of the resulting quantum circuits, a process that is commonly performed by so-called transpilation pipelines. One significant challenge in these pipelines is determining which optimizations to apply to a given circuit. This decision is usually based on fixed default configurations that are uniformly applied to all circuits, frequently resulting in missed opportunities for more aggressive circuit optimization. In this work, we tackle this challenge by applying autotuning with supervised machine learning to develop an automated method for selection of transpiler passes. To train our machine-learning models, we employ feature-model based sampling to generate a representative dataset that examines how different combinations of Qiskit transpiler passes perform across thousands of circuits drawn from the state-of-the-art benchmarking suite MQT Bench. Using these data, we build a predictive model extension for the Qiskit transpilation pipeline that uses a machine learning model to automatically select combinations of transpiler passes aiming to achieve a maximum reduction in two-qubit gates. Our empirical evaluation shows that the combinations selected by our model are never outperformed by Qiskit's optimization levels, achieve on average an additional 19.1% - 32.4% reduction in two-qubit gates, and for some circuits finds reductions of up to 95.8% in cases where Qiskit achieves no reduction at all.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block opti-mization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noisy simulations, and large-size circuits on analytical models. Our technique can be applied after existing optimizations to achieve higher circuit fidelity. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compiler optimizations such as t|ket). When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits, Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation tool chain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains to further improve the circuit fidelity.
Quantum compilation is a multi-pass process that translates a high-level circuit into an equivalent one executable on quantum hardware. A critical stage in this process is mapping, where additional gates are inserted to satisfy hardware constraints. Current mapping techniques often suffer from significant performance degradation—in terms of added gate count, increased circuit depth, and longer compilation times that scale with circuit size. In this work, we propose a novel methodology that enhances quantum compilation by leveraging concepts from Electronic Design Automation. Our approach partitions a quantum circuit into sub-circuits that can be compiled independently, and reformulates the mapping problem as a temporal floorplanning instance—a well-established technique in classical circuit design. We validate our method on widely used quantum circuit benchmark suites, achieving an average depth reduction of 22.05 % compared to traditional monolithic compilation chains using IBM Qiskit. Moreover, our approach reduces overall compilation time to that required for compiling the largest partition, while our partitioning-floorplanning algorithm runs, on average, two orders of magnitude faster than compiling the full circuit.
Quantum circuit compilation is a multi-stage process that translates a high-level quantum circuit representation into a sequence of quantum gates that can be directly executed by a quantum machine. One of the core steps in quantum compilation is mapping, a procedure that transforms a quantum circuit into a semantically equivalent circuit while inserting additional gates to comply with the architectural constraints of the underlying quantum hardware. Current mapping techniques exhibit significant performance degradation—in terms of circuit depth and gate count—when applied to large-scale circuits containing hundreds of thousands of gates or more. In this work, we propose a novel methodology to enhance quantum compiler capabilities by adapting general principles from classical Electronic Design Automation. We model the quantum hardware as being composed of standard cells, onto which portions of the circuit are mapped using a floorplanning-based technique. This contrasts with current state-of-the-art solutions, which perform mapping at the gate level without considering any form of hierarchical abstraction. We use the ChaCha20 stream cipher as a running example to validate and explain our strategy. We evaluate our methodology using two well-known, industrial-grade quantum compilers: IBM Qiskit and Quantinuum TKET. Compared to these compilers, our approach achieves an average circuit depth reduction of 59.78% and 68.85%, respectively, and a gate count reduction of 4.07 % and 6.20 %, respectively. These results are obtained across a large set of randomly generated quantum circuit descriptions in the range of millions of gates, with varying input and output connectivity for each block in the circuit.
We explore a method for automatically recompiling a quantum circuit A into a target circuit B , with the goal that both circuits have the same action on a specific input i.e. B ∣ i n ⟩ = A ∣ i n ⟩ . This is of particular relevance to hybrid, NISQ-era algorithms for dynamical simulation or eigensolving. The user initially specifies B as a blank template: a layout of parameterised unitary gates configured to the identity. The compilation then proceeds using quantum hardware to perform an isomorphic energy-minimisation task, and an optional gate elimination phase to compress the circuit. If B is insufficient for perfect recompilation then the method will result in an approximate solution. We optimise using imaginary time evolution, and a recent extension of quantum natural gradient for noisy settings. We successfully recompile a 7 -qubit circuit involving 186 gates of multiple types into an alternative form with a different topology, far fewer two-qubit gates, and a smaller family of gate types. Moreover we verify that the process is r o b u s t , finding that per-gate noise of up to 1 % can still yield near-perfect recompilation. We test the scaling of our algorithm on up to 20 qubits, recompiling into circuits with up to 400 parameterized gates, and incorporate a custom adaptive timestep technique. We note that a classical simulation of the process can be useful to optimise circuits for today's prototypes, and more generally the method may enable `blind' compilation i.e. harnessing a device whose response to control parameters is deterministic but unknown.The code and resources used to generate our results are openly available online \cite{githubLink} \cite{mmaGithubLink}. A simple Mathematica demonstration of our algorithm can be found at questlink.qtechtheory.org.