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arXiv:2104.01119 · Physical Review Applied

Hidden Inverses: Coherent Error Cancellation at the Circuit Level

Bichen Zhang, Swarnadeep Majumder, Pak Hong Leung, Stephen Crain, Ye Wang, Chao Fang, Dripto M. Debroy, Jungsang Kim, Kenneth R. Brown

Published Mar 30, 2022• 32 citations
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Abstract

Coherent gate errors are a concern in many proposed quantum-computing architectures. Here, we show that certain coherent errors can be reduced by a local optimization that chooses between two forms of the same Hermitian and unitary quantum gate. We refer to this method as hidden inverses, and it relies on constructing the same gate from either one sequence of physical operations or the inverted sequence of inverted operations. We use parity-controlled $Z$ rotations as our model circuit and numerically show the utility of hidden inverses as a function of circuit width $n$. We experimentally demonstrate the effectiveness for $n=2$ and $n=4$ qubits in a trapped-ion quantum computer. We numerically compare the method to other gate-level compilations for reducing coherent errors.

DOI
10.1103/physrevapplied.17.034074

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Coherent gate errors are a concern in many proposed quantum-computing architectures. Here, we show that certain coherent errors can be reduced by a local optimization that chooses between two forms of the same Hermitian and unitary quantum gate. We refer to this method as hidden inverses, and it relies on constructing the same gate from either one sequence of physical operations or the inverted sequence of inverted operations. We use parity-controlled ZZZ rotations as our model circuit and numerically show the utility of hidden inverses as a function of circuit width nnn. We experimentally demonstrate the effectiveness for n=2n=2n=2 and n=4n=4n=4 qubits in a trapped-ion quantum computer. We numerically compare the method to other gate-level compilations for reducing coherent errors.
Abstract We present a method to improve the convergence of variational algorithms based on hidden inverses (HIs) to mitigate coherent errors. In the context of error mitigation, this means replacing the hardware implementation of certain Hermitian gates with their inverses. Doing so results in noise cancellation and a more resilient quantum circuit. This approach improves performance in a variety of two-qubit error models where the noise operator also inverts with the gate inversion. We apply the mitigation scheme on superconducting quantum processors running the variational quantum eigensolver (VQE) algorithm to find the H 2 ground-state energy. When implemented on superconducting hardware we find that the mitigation scheme effectively reduces the energy fluctuations in the parameter learning path in VQE, reducing the number of iterations for a converged value. We also provide a detailed numerical simulation of VQE performance under different noise models and explore how HIs and randomized compiling affect the underlying loss landscape of the learning problem. These simulations help explain our experimental hardware outcomes, helping to connect lower-level gate performance to application-specific behavior in contrast to metrics like fidelity which often do not provide an intuitive insight into observed high level performance.
The success probability of a quantum algorithm constructed from noisy quantum gates cannot be accurately predicted from single-parameter metrics that compare noisy and ideal gates. We illustrate this concept by examining a system with coherent errors and comparing algorithm success rates for different choices of two-qubit gates that are constructed from composite pulse sequences, where the residual gate errors are related by a unitary transformation. As a result, all of the sequences have the same error relative to the ideal gate under any distance measure that is invariant under unitary transformations. However, the circuit success can vary dramatically by choosing error orientations that do not affect the final outcome and error orientations that cancel between conjugate controlled-nots, as demonstrated here with Clifford circuits, compiled Toffoli gates, and quantum simulation algorithms. The results point to the utility of both minimizing the error and optimizing the error direction and also to the advantages of using multiple control sequences for the same gate type within a single algorithm.
Quantum computing hardware is affected by quantum noise that undermine the quality of results of an executed quantum program. Amongst other quantum noises, coherent error that caused by parameter drifting and miscalibration, remains critical. While coherent error mitigation has been studied before, studies focused either on gate-level or pulse-level -- missing cross-level optimization opportunities; And most of them only target single-qubit gates -- while multi-qubit gates are also used in practice. To address above limitations, this work proposes a cross-layer approach for coherent error mitigation that considers program-level, gate-level, and pulse-level compiler optimizations, by leveraging the hidden inverse theory, and exploiting the structure inside different quantum programs, while also considering multi-qubit gates. We implemented our approach as compiler optimization passes, and integrated into IBM Qiskit framework. We tested our technique on real quantum computer (IBM-Brisbane), and demonstrated up to 92% fidelity improvements (45% on average), on several benchmarks.
Coherent errors are a dominant noise process in many quantum computing architectures. Unlike stochastic errors, these errors can combine constructively and grow into highly detrimental overrotations. To combat this, we introduce a simple technique for suppressing systematic coherent errors in low-density parity-check stabilizer codes, which we call stabilizer slicing. The essential idea is to slice low-weight stabilizers into two equally weighted Pauli operators and then apply them by rotating in opposite directions, causing their overrotations to interfere destructively on the logical subspace. With access to native gates generated by three-body Hamiltonians, we can completely eliminate purely coherent overrotation errors, and for overrotation noise of 0.99 unitarity we achieve a 135-fold improvement in the logical error rate of surface-17. For more conventional two-body ion trap gates, we observe an 89-fold improvement for Bacon-Shor-13 with purely coherent errors which should be testable in near-term fault-tolerance experiments. This second scheme takes advantage of the prepared gauge degrees of freedom, and to our knowledge is the first example in which the state of the gauge directly affects the robustness of a code's memory. This Letter demonstrates that coherent noise is preferable to stochastic noise within certain code and gate implementations when the coherence is utilized effectively.
Abstract Two-qubit gates are important components of quantum computing. However, unwanted interactions between qubits (so-called parasitic gates) can be particularly problematic and degrade the performance of quantum applications. In this work, we present two software methods to mitigate parasitic two-qubit gate errors. The first approach is built upon the Cartan’s KAK decomposition and keeps the original unitary decomposition for the error-free native two-qubit gate. It counteracts a parasitic two-qubit gate by only applying single-qubit rotations and therefore has no two-qubit gate overhead. We show the optimal choice of single-qubit mitigation gates. The second approach applies a numerical optimisation algorithm to re-compile a target unitary into the error-parasitic two-qubit gate plus single-qubit gates. We demonstrate these approaches on the CPhase-parasitic iSWAP-like gates. The KAK-based approach helps decrease unitary infidelity by a factor of 3 compared to the noisy implementation without error mitigation. When arbitrary single-qubit rotations are allowed, recompilation could completely mitigate the effect of parasitic errors but may require more native gates than the KAK-based approach. We also compare their average gate fidelity under realistic noise models, including relaxation and depolarising errors. Numerical results suggest that different approaches are advantageous in different error regimes, providing error mitigation guidance for near-term quantum computers.
We present a (REAS) technique to manage errors in quantum computers. Our method reduces the accumulation of errors in any quantum circuit composed of single- or two-qubit gates expressed as e − i σ θ for Pauli operators σ and θ ∈ [ 0 , π ) , which forms a universal gate set. For coherent errors, which include gate overrotation and crosstalk, we demonstrate a reduction of the error scaling in an L -depth circuit from O ( L ) to O ( L ) . This asymptotic error suppression behavior can be proven in a regime where all gates, including those constituting the error-suppressing protocol itself, are noisy. Going beyond coherent errors, we derive the general form of decoherence noise that can be suppressed by REAS. Lastly, we experimentally demonstrate the effectiveness of our approach regarding realistic errors using 100-qubit circuits with up to 64 two-qubit gate layers on IBM Quantum processors.