© 2020 Author(s). Lossy dielectrics are a significant source of decoherence in superconducting quantum circuits. In this report, we model and compare the dielectric loss in bulk and interfacial dielectrics in titanium nitride (TiN) and aluminum (Al) superconducting coplanar waveguide resonators. We fabricate isotropically trenched resonators to produce a series of device geometries that accentuate a specific dielectric region's contribution to the resonator quality factor. While each dielectric region contributes significantly to loss in TiN devices, the metal-air interface dominates the loss in the Al devices. Furthermore, we evaluate the quality factor of each TiN resonator geometry with and without a post-process hydrofluoric etch and find that it reduced losses from the substrate-air interface, thereby improving the quality factor.
Improving the performance of superconducting qubits and resonators generally results from a combination of materials and fabrication process improvements and design modifications that reduce device sensitivity to residual losses. One instance of this approach is to use trenching into the device substrate in combination with superconductors and dielectrics with low intrinsic losses to improve quality factors and coherence times. Here, we demonstrate titanium nitride coplanar waveguide resonators with mean quality factors exceeding two million and controlled trenching reaching 2.2 μm in the silicon substrate. Additionally, we measure sets of resonators with a range of sizes and trench depths and compare these results with finite-element simulations to demonstrate quantitative agreement with a model of interface dielectric loss. We then apply this analysis to determine the extent to which trenching can improve resonator performance.
We systematically investigate the influence of the fabrication process on dielectric loss in aluminum-on-silicon superconducting coplanar waveguide resonators with internal quality factors (Qi) of about one million at the single-photon level. These devices are essential components in superconducting quantum processors; they also serve as proxies for understanding the energy loss of superconducting qubits. By systematically varying several fabrication steps, we identify the relative importance of reducing loss at the substrate–metal and substrate–air interfaces. We find that it is essential to clean the silicon substrate in hydrogen fluoride (HF) prior to aluminum deposition. A post-fabrication removal of the oxides on the surface of the silicon substrate and the aluminum film by immersion in HF further improves the Qi. We observe a small, but noticeable, adverse effect on the loss by omitting either standard cleaning (SC1), pre-deposition heating of the substrate to 300 °C, or in situ post-deposition oxidation of the film’s top surface. We find no improvement due to excessive pumping meant to reach a background pressure below 6 × 10−8 mbar. We correlate the measured loss with microscopic properties of the substrate–metal interface through characterization with x-ray photoelectron spectroscopy, time-of-flight secondary ion mass spectrometry, transmission electron microscopy, energy-dispersive x-ray spectroscopy, and atomic force microscopy.
Material losses in superconducting circuits fundamentally limit qubit coherence times and resonator quality factors. Most research efforts focus on mitigating losses at circuit interfaces, including metal--substrate, substrate--air, and metal--air interfaces. However, the correlation between TLS and non-TLS losses with the intrinsic properties of the superconducting metal and the dielectric edge smoothness is not well studied. In this work, we link the aluminum film grain size to non-TLS losses and the dielectric trimming profile and roughness to TLS loss; both loss mechanisms are subsequently mitigated. To reduce metal-related losses, we engineer the aluminum microstructure by heating during deposition, increasing grain size and reducing grain boundary density. Beyond mitigating metal losses, we introduce a two-step etching technique, Tropic etching, to suppress dielectric TLS loss by producing an ultra-smooth silicon surface with minimal defects and redeposition. These results lay out the fabrication pathway for aluminum resonators with lower loss, demonstrating two-orders-of-magnitude improvement in quality factor from
6×104 to
2.3×106. Since aluminum is the basis for most high-coherence Josephson junctions and dielectric edges are inherent to all common device geometries, the improvements in aluminum microstructure and edge profiling, presented here, can enhance the performance of superconducting quantum devices.
© 2019 American Physical Society. Superconducting quantum-computing architectures comprise resonators and qubits that experience energy loss due to two-level systems (TLSs) in bulk and interfacial dielectrics. An understanding of these losses is critical to improving performance in superconducting circuits. In this work, we present a method for quantifying the TLS losses of different bulk and interfacial dielectrics present in superconducting coplanar-waveguide (CPW) resonators. By combining statistical characterization of sets of specifically designed CPW resonators on isotropically etched silicon substrates with detailed electromagnetic modeling, we determine the separate loss contributions from individual material interfaces and bulk dielectrics. This technique for analyzing interfacial TLS losses can be used to guide targeted improvements to qubits, resonators, and their superconducting fabrication processes.
We report on the fabrication and characterization of superconducting coplanar waveguide (CPW) resonators based on titanium nitride (TiN) thin films deposited on 200\,mm diameter high-resistivity Si(100) substrates. We systematically investigate how deposition conditions, dry-etch power and in-situ resist strip temperature affect morphology, superconducting properties and dielectric losses. By tuning reactive sputtering conditions, three distinct preferred out-of-plane crystal orientations - (111), (200), and a mix of both are achieved. Our results demonstrate that all films exhibit similar minimal two-level system (TLS) losses, with TiN111 exhibiting the lowest median TLS losses
δ~TLS, and greater robustness against reoxidation. The applied structuring process, in contrast, has a far greater influence on the TLS loss than the crystal orientation of the TiN film and, consequently, the intrinsic material properties of the superconducting layer. The lowest TLS losses for all TiN depositions were achieved with a low power etch and low temperature resist strip. An additional buffered oxide etch (BOE) treatment could remove high-loss interfacial oxides at the metal-air (MA) and substrate-air (SA) interface and recover the etch-induced TLS losses. Consequently, TiN resonators exhibiting
δ~TLS values as low as
9.67×10−7 were realized. The corresponding median low-power loss,
δ~LP, amounts to
11.04×10−7, which translates to an internal quality factor approaching one million. These findings highlight the critical role of process induced oxide formation at the MA and SA interfaces in limiting the performance of TiN resonators and provide a scalable, low-loss process compatible with industry-grade 200\,mm CMOS qubit fabrication workflows.