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arXiv:2006.14103 · Lecture notes in computer science

Simulation Methodology for Electron Transfer in CMOS Quantum Dots

Andrii Sokolov, Dmytro Mishagli, Panagiotis Giounanlis, Imran Bashir, Dirk Leipold, Eugene Koskin, Robert Bogdan Staszewski, Elena Blokhina

Published Jan 1, 2020• 7 citations
arXivHTMLPDF
DOI
10.1007/978-3-030-50433-5_50

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Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circuits. Here we demonstrate the integration of a single-electron charge storage CMOS quantum dot with a CMOS transistor for control of the readout via gate-based dispersive sensing using a lumped element LCLCLC resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully-depleted silicon-on-insulator technology. We obtain a charge sensitivity of δq=165 μeHz−1/2δq=165\, μe \mathrm{Hz}^{-1/2}δq=165μeHz−1/2 when the quantum dot readout is enabled by the control FET. Additionally, we observe a single-electron retention time of the order of a second when storing a single-electron charge on the quantum dot at milli-Kelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive qubit readout in CMOS technology opening the path for the development of an all-silicon quantum-classical processor.
We report progress toward the development of a quantum silicon-on-insulator (QSOI(R)) technology compatible with 300mm CMOS fabrication and adapted from the 28nm Fully-Depleted SOI (28nm FD-SOI) platform for scalable quantum computing. We compare quantum devices fabricated with standard 28nm FD-SOI and QSOI(R) technologies, and show striking improvements of room temperature electrostatic properties of the individual device. Moreover, the QSOI(R) technology has significantly reduced the device variability and the dispersion of device properties at the wafer level. Transistor metrics are reproduced by TCAD simulations showing that the electrostatics of the devices behave as expected for QSOI(R) technology. Wafer-scale measurements at sub-2K show reproducible quantum dots down to the few-electron regime with 69\% yield for successful charge detection of the first electron and a dispersion of the first electron position of ±35mV\mathrm{\pm 35 mV}±35mV over 377 quantum dots. These results establish QSOI(R) as a promising platform for CMOS-compatible quantum device co-integration.