We propose an efficient heuristic for mapping the logical qubits of quantum algorithms to the physical qubits of connectivity-limited devices, adding a minimal number of connectivity-compliant SWAP gates. In particular, given a quantum circuit, we construct an undirected graph with edge weights a function of the two-qubit gates of the quantum circuit. Taking inspiration from spectral graph drawing, we use an eigenvector of the graph Laplacian to place logical qubits at coordinate locations. These placements are then mapped to physical qubits for a given connectivity. We primarily focus on one-dimensional connectivities and sketch how the general principles of our heuristic can be extended for use in more general connectivities.
We propose an efficient heuristic for mapping the logical qubits of quantum algorithms to the physical qubits of connectivity-limited devices, adding a minimal number of connectivity-compliant SWAP gates. In particular, given a quantum circuit, we construct an undirected graph with edge weights a function of the two-qubit gates of the quantum circuit. Taking inspiration from spectral graph drawing, we use an eigenvector of the graph Laplacian to place logical qubits at coordinate locations. These placements are then mapped to physical qubits for a given connectivity. We primarily focus on one-dimensional connectivities and sketch how the general principles of our heuristic can be extended for use in more general connectivities.
Abstract In some quantum technologies, an interaction is only allowed between physically adjacent qubits, hence the nearest-neighbor requirement is needed. In such technologies, quantum gates are limited to operate on adjacent qubits. To make a quantum circuit compliant with the nearest-neighbor requirement, SWAP gates are inserted into the circuit to move the interacting qubits of a gate to be adjacent to each other. The mapping of qubits on the physical environment has an important role on reducing the number of SWAP gates and thus the circuit latency. Focusing on this issue, in this paper, a method is proposed that maps a quantum circuit onto a 3D physical hardware such as a 3D optical lattice. A new methodology for this mapping problem is proposed based on a complex network spectral clustering algorithm and graph theory, which are suitable for very large scale networks. It includes three steps: finding the order of qubit mapping, placing physical qubits, and routing. Simulation results show that the proposed mapping approach not only decreases the average number of SWAP gates by about 37% but also improves the average runtime by about 87% for the 2D architecture compared to PAQCS. Moreover, it reduces the average number of SWAP gates for the 3D architecture by 17.1% compared to the best studies in the literatures.
Mapping logical quantum circuits to Noisy Intermediate-Scale Quantum (NISQ) devices is a challenging problem which has attracted rapidly increasing interests from both quantum and classical computing communities. This article proposes an efficient method by (i) selecting an initial mapping that takes into consideration the similarity between the architecture graph of the given NISQ device and a graph induced by the input logical circuit and (ii) searching, in a filtered and depth-limited way, a most usefulswapcombination that makes executable as many as possible two-qubit gates in the logical circuit. The proposed circuit transformation algorithm can significantly decrease the number of auxiliary two-qubit gates required to be added to the logical circuit, especially when it has a large number of two-qubit gates. For an extensive benchmark set of 131 circuits and IBM's current premium Q system, viz., IBM Q Tokyo, our algorithm needs, in average, 0.3801 extra two-qubit gates per input two-qubit gate, while the corresponding figures for three state-of-the-art algorithms are 0.4705, 0.8154, and 1.0066, respectively.
Rapid progress in the physical implementation of quantum computers gave birth to multiple recent quantum machines implemented with superconducting technology. In these NISQ machines, each qubit is physically connected to a bounded number of neighbors. This limitation prevents most quantum programs from being directly executed on quantum devices. A compiler is required for converting a quantum program to a hardware-compliant circuit, in particular, making each two-qubit gate executable by mapping the two logical qubits to two physical qubits with a link between them. To solve this problem, existing studies focus on inserting SWAP gates to dynamically remap logical qubits to physical qubits. However, most of the schemes lack the consideration of time-optimality of generated quantum circuits, or are achieving time-optimality with certain constraints. In this work, we propose a theoretically time-optimal SWAP insertion scheme for the qubit mapping problem. Our model can also be extended to practical heuristic algorithms. We present exact analysis results by using our model for quantum programs with recurring execution patterns. We have for the first time discovered an optimal qubit mapping pattern for quantum fourier transformation (QFT) on 2D nearest neighbor architecture. We also present a scalable extension of our theoretical model that can be used to solve qubit mapping for large quantum circuits.
The qubit-mapping problem aims to assign qubits from a quantum circuit to a realistic NISQ device in order to maximize limited resources. Many algorithmic solutions for the qubit-mapping problem have been introduced, but much work remains in order to evaluate the effectiveness of a qubit-mapping algorithm with respect to mapping a circuit to devices while taking into account the noise characteristics of the device. In this work, we make progress on this question. Firstly, we introduce a noise-aware heuristic mapping algorithm which fares well when compared to brute-force and trivial mapping solutions for several benchmarks. This comparison serves to provide effective upper and lower bounds for our heuristic mapper in terms of an algorithm's success rate. Subsequently, we analyze how the performance of the mapping algorithm is affected by the characteristics of the interaction graph, which represents the interactions of qubits in a quantum circuit. We observe that as interaction-graph edges are added to benchmarks in either depth-first or breadth-first fashion, our heuristic algorithm's calculated success rate varies significantly, implying that both the amount of interaction-graph vertex degree and the distribution of edges in a quantum circuit's interaction graph play a significant role in the calculated success rate when our greedy heuristic maps to a quantum device's coupling graph. Lastly, we discovered that our heuristic algorithm provides substantial benefits over the trivial solution when mapping quantum circuits to QPUs, provided that less than approximately 75\% of the QPU is occupied. Lastly, as the size of the quantum processor in our simulation grows, so do the purported benefits from utilizing our heuristic mapper. This work takes the first steps towards the characterization of quantum algorithms with respect to efficient qubit-mapping solutions in NISQ-era devices.
Abstract Currently available quantum computing hardware platforms have limited 2-qubit connectivity among their addressable qubits. In order to run a generic quantum algorithm on such a platform, one has to transform the initial logical quantum circuit describing the algorithm into an equivalent one that obeys the connectivity restrictions. In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by { CNOT , R Z } and outputs a circuit that respects the connectivity of the device. As a concrete application, we apply our techniques to Google’s Bristlecone 72-qubit quantum chip connectivity, IBM’s Tokyo 20-qubit quantum chip connectivity, and Rigetti’s Acorn 19-qubit quantum chip connectivity. In addition, we also compare the performance of our scheme as a function of sparseness of randomly generated quantum circuits, and discuss how to apply our techniques as a subroutine for the more general mapping problem over universal set of gates (Clifford + T).
In near-term quantum computing devices, connectivity between qubits remain limited by architectural constraints. A computational circuit with given connectivity requirements necessary for multiqubit gates has to be embedded within physical hardware with fixed connectivity. Long-distance gates have to be done by first routing the relevant qubits together. The simplest routing strategy involves the use of gates to swap the information carried by two unconnected qubits to connected ones. Ideal gates just permute the qubits; real gates, however, have the added possibilities of causing simultaneous errors on the qubits involved and spreading errors across the circuit. A general swap scheme thus changes the error-propagation properties of a circuit, including those necessary for fault-tolerant functioning of a circuit. Here, we present a simple strategy to design the swap scheme needed to embed an arbitrary circuit onto a physical hardware with constrained connectivity, in a manner that preserves the fault-tolerant properties of the abstract circuit. Our approach is generally applicable, and works on any circuit, including ones that carry out logical operations and error correction. The embedded circuit will, of course, be noisier, compared to a native implementation of the abstract circuit, but we show in the examples of embedding surface codes on heavy-hexagonal and hexagonal lattices that the deterioration is not severe. This then offers a straightforward solution to implementing circuits with fault-tolerance properties on current hardware.