In near-term quantum computing devices, connectivity between qubits remain limited by architectural constraints. A computational circuit with given connectivity requirements necessary for multiqubit gates has to be embedded within physical hardware with fixed connectivity. Long-distance gates have to be done by first routing the relevant qubits together. The simplest routing strategy involves the use of gates to swap the information carried by two unconnected qubits to connected ones. Ideal gates just permute the qubits; real gates, however, have the added possibilities of causing simultaneous errors on the qubits involved and spreading errors across the circuit. A general swap scheme thus changes the error-propagation properties of a circuit, including those necessary for fault-tolerant functioning of a circuit. Here, we present a simple strategy to design the swap scheme needed to embed an arbitrary circuit onto a physical hardware with constrained connectivity, in a manner that preserves the fault-tolerant properties of the abstract circuit. Our approach is generally applicable, and works on any circuit, including ones that carry out logical operations and error correction. The embedded circuit will, of course, be noisier, compared to a native implementation of the abstract circuit, but we show in the examples of embedding surface codes on heavy-hexagonal and hexagonal lattices that the deterioration is not severe. This then offers a straightforward solution to implementing circuits with fault-tolerance properties on current hardware.
In near-term quantum computing devices, connectivity between qubits remain limited by architectural constraints. A computational circuit with given connectivity requirements necessary for multiqubit gates has to be embedded within physical hardware with fixed connectivity. Long-distance gates have to be done by first routing the relevant qubits together. The simplest routing strategy involves the use of gates to swap the information carried by two unconnected qubits to connected ones. Ideal gates just permute the qubits; real gates, however, have the added possibilities of causing simultaneous errors on the qubits involved and spreading errors across the circuit. A general swap scheme thus changes the error-propagation properties of a circuit, including those necessary for fault-tolerant functioning of a circuit. Here, we present a simple strategy to design the swap scheme needed to embed an arbitrary circuit onto a physical hardware with constrained connectivity, in a manner that preserves the fault-tolerant properties of the abstract circuit. Our approach is generally applicable, and works on any circuit, including ones that carry out logical operations and error correction. The embedded circuit will, of course, be noisier, compared to a native implementation of the abstract circuit, but we show in the examples of embedding surface codes on heavy-hexagonal and hexagonal lattices that the deterioration is not severe. This then offers a straightforward solution to implementing circuits with fault-tolerance properties on current hardware.
Quantum computing is a field that shows tremendous possibilities and promise. It can provide an exponential speedup compared to classical computers in many computational problems, including simulations of general quantum mechanical systems, pattern finding and solving linear systems. Quantum computations can be performed by making use of qubits and performing operations, called gates, on them. A physical realisation of a qubit will be faulty, and to combat the errors that will inadvertently but unavoidably occur, the use of a quantum error correction code (QECC) is needed. A QECC is able to correct static errors; errors that occur on the states. However, it can not correct errors that occur on and during the operations. To make the computer resilient to these errors, the implementation of the QECC has to be performed fault-tolerantly. A fault-tolerant implementation of a quantum operation is designed in such a way that errors that happen during the operation, through faulty gates, do not propagate to errors on the states that are not correctable any more by the QECC. Hence, error propagation is a key concept in fault-tolerance. Every element of a general quantum circuit needs to be designed fault-tolerant. One of the elements that will be needed in any realistic quantum computer architecture is the possibility of exchanging the states of two qubits, so that an arbitrary pair of qubits can be brought physically close, allowing the implementation of multi-qubit gates. Exchanging the states of two qubits can be performed by a fault-tolerant SWAP gate, that makes use of one ancilla qubit. In this thesis, a fault-tolerant SWAP operation is implemented on the IBM 5-qubit ‘Tenerife’ device. It is characterized as a quantum channel by performing quantum process tomography (QPT). The CPTP constraints of quantum channels in the framework of QPT are discussed and a method of obtaining a CPTP estimate of an initial QPT reconstruction is given. The error process of the fault-tolerant SWAP is analysed and subsequently compared to a normal implementation of the SWAP gate, on which tomography is performed as well. The main measure that is used in the comparison is the ratio r of multi-qubit errors (or correlated) to single-qubit (or uncorrelated) errors in the two implementations. SPAM errors are an important source of estimated infidelity. To filter these SPAM errors and obtain a better estimate of only the circuits, SPAM errors are approximated to be only measurement errors. The errors are characterized by performing tomography on an arbitrary short identity channel, and subsequently using this as an estimate of the measurement error map. This gives a method to estimate a representation of the circuit itself. We can report on an error ratio r of 0.170±0.0029 for the fault-tolerant SWAP operation and an error ratio r of 1.256 ± 0.0129 for the non-fault-tolerant SWAP operation. However, the total error in the fault-tolerant SWAP is much higher, resulting in a process fidelity Fp = 0.608 for the fault-tolerant implementation and Fp = 0.742 for the normal implementation. This is due to the larger number of gates in the fault-tolerant circuit. This research shows that a SWAP operation can be implemented fault-tolerantly, but that the error rates of the devices need to be reduced before their use becomes viable.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
Quantum error correction is a crucial tool for mitigating hardware errors in quantum computers by encoding logical information into multiple physical qubits. However, no single error-correcting code allows for an intrinsically fault-tolerant implementation of all the gates needed for universal quantum computing [1-3]. One way to tackle this problem is to switch between two suitable error-correcting codes, while preserving the encoded logical information, which in combination give access to a fault-tolerant universal gate set [4-6]. In this work, we present the first experimental implementation of fault-tolerant code switching between two codes. One is the seven-qubit color code [7], which features fault-tolerant CNOT and H quantum gates, while the other one, the 10-qubit code [8], allows for a fault-tolerant T-gate implementation. Together they form a complementary universal gate set. Building on essential code switching building blocks, we construct logical circuits and prepare 12 different logical states which are not accessible natively in a fault-tolerant way within a single code. Finally, we use code switching to entangle two logical qubits employing the full universal gate set in a single logical quantum circuit. Our results experimentally open up a new route towards deterministic control over logical qubits with low auxiliary qubit overhead, not relying on the probabilistic preparation of resource states.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilizers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.
We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.