In previous work, we proposed a method for leveraging efficient classical simulation algorithms to aid in the analysis of large-scale fault-tolerant circuits implemented on hypothetical quantum information processors. Here, we extend those results by numerically studying the efficacy of this proposal as a tool for understanding the performance of an error-correction gadget implemented with fault models derived from physical simulations. Our approach is to approximate the arbitrary error maps that arise from realistic physical models with errors that are amenable to a particular classical simulation algorithm in an ``honest'' way; that is, such that we do not underestimate the faults introduced by our physical models. In all cases, our approximations provide an ``honest representation'' of the performance of the circuit composed of the original errors. This numerical evidence supports the use of our method as a way to understand the feasibility of an implementation of quantum information processing given a characterization of the underlying physical processes in experimentally accessible examples.
In previous work, we proposed a method for leveraging efficient classical simulation algorithms to aid in the analysis of large-scale fault-tolerant circuits implemented on hypothetical quantum information processors. Here, we extend those results by numerically studying the efficacy of this proposal as a tool for understanding the performance of an error-correction gadget implemented with fault models derived from physical simulations. Our approach is to approximate the arbitrary error maps that arise from realistic physical models with errors that are amenable to a particular classical simulation algorithm in an honest'' way; that is, such that we do not underestimate the faults introduced by our physical models. In all cases, our approximations provide an honest representation'' of the performance of the circuit composed of the original errors. This numerical evidence supports the use of our method as a way to understand the feasibility of an implementation of quantum information processing given a characterization of the underlying physical processes in experimentally accessible examples.
Understanding the performance of realistic noisy encoded circuits is an important task for the development of large-scale practical quantum computers. Specifically, the development of proposals for quantum computation must be well informed by both the qualities of the low-level physical system of choice, and the properties of the high-level quantum error correction and fault-tolerance schemes. Gaining insight into how a particular computation will play out on a physical system is in general a difficult problem, as the classical simulation of arbitrary noisy quantum circuits is inefficient. Nevertheless, important classes of noisy circuits can be simulated efficiently. Such simulations have led to numerical estimates of threshold errors rates and resource estimates in topological codes subject to efficiently simulable error models. \n \nThis thesis describes and analyzes a method that my collaborators and I have introduced for leveraging efficient simulation techniques to understand the performance of large quantum processors that are subject to errors lying outside of the efficient simulation algorithm's applicability. The idea is to approximate an arbitrary gate error with an error from the efficiently simulable set in a way that ``honestly'' represents the original error's ability to preserve or distort quantum information. After introducing and analyzing the individual gate approximation method, its utility as a means for estimating circuit performance is studied. In particular, the method is tested within the use-case for which it was originally conceived; understanding the performance of a hypothetical physical implementation of a quantum error-correction protocol. It is found that the method performs exactly as desired in all cases. That is, the circuits composed of the approximated error models honestly represent the circuits composed of the errors derived from the physical models.
Understanding fault-tolerant properties of quantum circuits is important for designing large-scale quantum information processors. In particular, simulating properties of encoded circuits is a crucial tool for investigating the relationship between properties such as the noise model, encoding scheme, and threshold value. For general noisy circuits, these simulations quickly become intractable in the size of the encoded circuit. We introduce a general theoretical method for approximating a noise process by one that allows for efficient Monte Carlo simulation of properties of encoded circuits. The approximation is as close to the original process as possible without overestimating its ability to preserve quantum information, a key property for obtaining honest estimates of threshold values. We numerically illustrate the method with various physically relevant noise models.
A reliable large-scale quantum computer would be able to solve problems in physics and chemistry exponentially faster than current classical processors. A large-scale quantum device has not been built because quantum systems are naturally sensitive to environmental influences which manifest as errors in memory and operations during computation. For a large-scale device to become a reality, protocols must be developed that reduce the influence of errors during computation in a manner that maintains scalability of the device. This scalability criteria requires the protocols developed to handle errors must be implemented in a way such that the size of the quantum system and number of operations grows in a tractable manner. Furthermore, the sources of errors must be modeled accurately for true assessments of the viability of these protocols. In this dissertation, we present an investigation into methods of performing reliable quantum computation in the presence of errors in small quantum systems (< 50 qubits). These methods should be considered as software primitives used to built reliable large-scale quantum algorithms and quantum memories. These methods occur in two flavors: quantum error correction and fault-tolerant operations. For quantum error correction, we perform assessments of error correction in the presence of error sources indicative of ion trap quantum computers. For fault-tolerant operations, we investigate the quantum resource cost and efficacy of implementing various techniques for performing reliable operations that would allow for a quantum advantange in a large-scale device.
A universal, scalable quantum computer will require the use of quantum error correction in order to achieve fault tolerance. The assessment and comparison of error-correcting strategies is performed by classical simulation. However, due to the prohibitive exponential scaling of general quantum circuits, simulations are restrained to specific subsets of quantum operations. This creates a gap between accuracy and efficiency which is particularly problematic when modeling noise, because most realistic noise models are not efficiently simulable on a classical computer. We have introduced extensions to the Pauli channel, the traditional error channel employed to model noise in simulations of quantum circuits. These expanded error channels are still computationally tractable to simulate, but result in more accurate approximations to realistic error channels at the single qubit level. Using the Steane [[7,1,3]] code, we have also investigated the behavior of these expanded channels at the logical error-corrected level. We have found that it depends strongly on whether the error is incoherent or coherent. In general, the Pauli channel will be an excellent approximation to incoherent channels, but an unsatisfactory one for coherent channels, especially because it severely underestimates the magnitude of the error. Finally, we also studied the honesty and accuracy of the expanded channels at the logical level. Our results suggest that these measures can be employed to generate lower and upper bounds to a quantum code's threshold under the influence of a specific error channel.
Quantum algorithms are often represented in terms of quantum circuits operating on ideal (logical) qubits. However, the practical implementation of these algorithms poses significant challenges. Many quantum algorithms require a substantial number of logical qubits, and the inherent susceptibility to errors of quantum computers require quantum error correction. The integration of error correction introduces overhead in terms of both space (physical qubits required) and runtime (how long the algorithm needs to be run for). This paper addresses the complexity of comparing classical and quantum algorithms, primarily stemming from the additional quantum error correction overhead. We propose a comprehensive framework that facilitates a direct and meaningful comparison between classical and quantum algorithms. By acknowledging and addressing the challenges introduced by quantum error correction, our framework aims to provide a clearer understanding of the comparative performance of classical and quantum computing approaches. This work contributes to understanding the practical viability and potential advantages of quantum algorithms in real-world applications. We apply our framework to quantum cryptanalysis, since it is well known that quantum algorithms can break factoring and discrete logarithm based cryptography and weaken symmetric cryptography and hash functions. In order to estimate the real-world impact of these attacks, apart from tracking the development of fault-tolerant quantum computers it is important to have an estimate of the resources needed to implement these quantum attacks. This analysis provides state-of-the art snap-shot estimates of the realistic costs of implementing quantum attacks on these important cryptographic algorithms, assuming quantum fault-tolerance is achieved using surface code methods, and spanning a range of potential error rates. These estimates serve as a guide for gauging the realistic impact of these algorithms and for benchmarking the impact of future advances in quantum algorithms, circuit synthesis and optimization, fault-tolerance methods and physical error rates.
Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.
We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.
Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor's factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor's algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.