arXiv:0907.3757 · Superconductor Science and Technology
A scalable control system for a superconducting adiabatic quantum optimization processor
Mark W. Johnson, P. Bunyk, F. Maibaum, E. Tolkacheva, A. J. Berkley, E. M. Chapple, R. Harris, J Johansson, Trevor M. Lanting, I. Perminov, E. Ladizinsky, T. Oh, Geordie Rose
We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines.
We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines.
Quantum processors have the potential to accelerate specific computing tasks but are difficult to scale up due to engineering limitations, such as the number of available cables and cooling power for dilution refrigerators for quantum bits (qubits). Hence, it is very important to develop scalable, energy-efficient interface circuits that can control many qubits via a few control lines inside a dilution refrigerator. One of the most important interface circuits is the flux controller (FC), which generates arbitrary dc flux bias to adjust the characteristics of component devices such as qubits. In this paper, we propose and demonstrate FCs using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. We develop two types of FCs: the AQFP FC and the AQFP/single-flux-quantum (AQFP/SFQ) FC. Both FCs require only a few control lines and have extremely small power dissipation, thus exhibiting high scalability. Furthermore, the AQFP/SFQ FC can control flux bias using ballistic SFQ transmission, which is crucial for integration with qubits. As a proof of concept, we demonstrate AQFP and AQFP/SFQ FCs at 4.2 K, fabricated by the AIST high-speed standard process. Our results indicate that AQFP logic is highly suitable for use as qubit interface circuits for very large-scale quantum processors, especially from the viewpoint of the control line count, power dissipation, and amount of supply currents.
A superconducting chip containing a regular array of flux qubits, tunable interqubit inductive couplers, an XY-addressable readout system, on-chip programmable magnetic memory, and a sparse network of analog control lines has been studied. The architecture of the chip and the infrastructure used to control it were designed to facilitate the implementation of an adiabatic quantum optimization algorithm. The performance of an eight-qubit unit cell on this chip has been characterized by measuring its success in solving a large set of random Ising spin-glass problem instances as a function of temperature. The experimental data are consistent with the predictions of a quantum mechanical model of an eight-qubit system coupled to a thermal environment. These results highlight many of the key practical challenges that we have overcome and those that lie ahead in the quest to realize a functional large-scale adiabatic quantum information processor.
We report the development of flux memory for use with superconducting circuits. This technology stores persistent currents in superconducting loops on-chip to be used to provide flux biasing for superconducting circuits, like qubits. We developed three types of flux memory and draw comparisons among them for circuit design. We demonstrate the utility of flux memory by using an in-situ flux detector and characterize each approach and further demonstrate that once flux is set in a memory cell, benchtop DC control sources can be powered off, leaving the on-chip flux bias in place. We propose that flux memory can be arranged in a two-dimensional configuration to multiplex control signals and reduce how line counts scale (N^2 devices -> 2N control lines), and our experimental results pave the path to the proposed scalability. We demonstrate the use of flux memory to flux bias a transmon qubit and show the tunability of the qubit state to a target frequency which remained stable on-chip for 20 hours.
We have designed, fabricated and tested an XY-addressable readout system that is specifically tailored for the reading of superconducting flux qubits in an integrated circuit that could enable adiabatic quantum optimization. In such a system, the flux qubits only need to be read at the end of an adiabatic evolution when quantum mechanical tunneling has been suppressed, thus simplifying many aspects of the readout process. The readout architecture for an N-qubit adiabatic quantum optimization system comprises N hysteretic dc SQUIDs and N rf SQUID latches controlled by 2N+2 bias lines. The latching elements are coupled to the qubits and the dc SQUIDs are then coupled to the latching elements. This readout scheme provides two key advantages: First, the latching elements provide exceptional flux sensitivity that significantly exceeds what may be achieved by directly coupling the flux qubits to the dc SQUIDs using a practical mutual inductance. Second, the states of the latching elements are robust against the influence of ac currents generated by the switching of the hysteretic dc SQUIDs, thus allowing one to interrogate the latching elements repeatedly so as to mitigate the effects of stochastic switching of the dc SQUIDs. We demonstrate that it is possible to achieve single qubit read error rates of <10−6 with this readout scheme. We have characterized the system-level performance of a 128-qubit readout system and have measured a readout error probability of 8×10−5 in the presence of optimal latching element bias conditions.
Scaling superconducting quantum processors is increasingly constrained by the wiring, heat load, and calibration overhead associated with delivering high-resolution analog signals from room temperature to qubits at millikelvin temperature. Here we demonstrate a superconducting digital-to-analog converter (DAC) integrated with high-coherence fluxonium qubits in a multi-chip module architecture. The DACs generate persistent analog flux signals for tuning qubit parameters and are programmed deterministically using single-flux-quantum (SFQ) pulses, providing a digital interface compatible with established SFQ routing and demultiplexing technologies. Operating at millikelvin temperature, the DACs enable in-situ tuning of fluxonium qubits without measurable degradation of qubit coherence. The presented device provides a static control primitive for flux-tunable qubits, enabling parameter homogenization and eliminating the need for individual room-temperature DC bias lines. These results establish SFQ-programmable millikelvin DACs as a building block for digitally controlled superconducting quantum processors.
We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).