Experimental investigation of an eight-qubit unit cell in a superconducting optimization processor
R. Harris, Mark W. Johnson, Trevor M. Lanting, A. J. Berkley, J. Johansson, P. Bunyk, E. Tolkacheva, E. Ladizinsky, N. Ladizinsky, T. Oh, Florentin Cioată, I. Perminov, P. Spear, Colin Enderud, Chris C. Rich, Sergey V. Uchaikin, M. C. Thom, E. M. Chapple, J. Wang, B. Wilson, M. H. S. Amin, Neil G. Dickson, Kamran Karimi, B. Macready, C. J. S. Truncik, Geordie Rose
A superconducting chip containing a regular array of flux qubits, tunable interqubit inductive couplers, an XY-addressable readout system, on-chip programmable magnetic memory, and a sparse network of analog control lines has been studied. The architecture of the chip and the infrastructure used to control it were designed to facilitate the implementation of an adiabatic quantum optimization algorithm. The performance of an eight-qubit unit cell on this chip has been characterized by measuring its success in solving a large set of random Ising spin-glass problem instances as a function of temperature. The experimental data are consistent with the predictions of a quantum mechanical model of an eight-qubit system coupled to a thermal environment. These results highlight many of the key practical challenges that we have overcome and those that lie ahead in the quest to realize a functional large-scale adiabatic quantum information processor.
A superconducting chip containing a regular array of flux qubits, tunable interqubit inductive couplers, an XY-addressable readout system, on-chip programmable magnetic memory, and a sparse network of analog control lines has been studied. The architecture of the chip and the infrastructure used to control it were designed to facilitate the implementation of an adiabatic quantum optimization algorithm. The performance of an eight-qubit unit cell on this chip has been characterized by measuring its success in solving a large set of random Ising spin-glass problem instances as a function of temperature. The experimental data are consistent with the predictions of a quantum mechanical model of an eight-qubit system coupled to a thermal environment. These results highlight many of the key practical challenges that we have overcome and those that lie ahead in the quest to realize a functional large-scale adiabatic quantum information processor.
We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).
In the pursuit of scalable superconducting quantum computing, tunable couplers have emerged as a pivotal component, offering the flexibility required for complex quantum operations of high performance. In most current architectures of superconducting quantum chips, such couplers are not equipped with dedicated readout circuits to reduce complexity in both design and operation. However, this strategy poses challenges in precise characterization, calibration, and control of the couplers. In this work, we develop a hardware-efficient and robust technique based on adiabatic control to address this issue. The critical ingredient of this technique is adiabatic swap operation between a tunable coupler and nearby qubits. Using this technique, we have characterized and calibrated tunable couplers in our chips and achieved straightforward and precise control over these couplers. For example, we have demonstrated the calibration and correction of the flux distortion of couplers. In addition, we have also expanded this technique to tune the dispersive shift between a frequency-fixed qubit and its readout resonator over a wide range.
We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines.
We have designed, fabricated and tested an XY-addressable readout system that is specifically tailored for the reading of superconducting flux qubits in an integrated circuit that could enable adiabatic quantum optimization. In such a system, the flux qubits only need to be read at the end of an adiabatic evolution when quantum mechanical tunneling has been suppressed, thus simplifying many aspects of the readout process. The readout architecture for an N-qubit adiabatic quantum optimization system comprises N hysteretic dc SQUIDs and N rf SQUID latches controlled by 2N+2 bias lines. The latching elements are coupled to the qubits and the dc SQUIDs are then coupled to the latching elements. This readout scheme provides two key advantages: First, the latching elements provide exceptional flux sensitivity that significantly exceeds what may be achieved by directly coupling the flux qubits to the dc SQUIDs using a practical mutual inductance. Second, the states of the latching elements are robust against the influence of ac currents generated by the switching of the hysteretic dc SQUIDs, thus allowing one to interrogate the latching elements repeatedly so as to mitigate the effects of stochastic switching of the dc SQUIDs. We demonstrate that it is possible to achieve single qubit read error rates of <10−6 with this readout scheme. We have characterized the system-level performance of a 128-qubit readout system and have measured a readout error probability of 8×10−5 in the presence of optimal latching element bias conditions.
As quantum information processors grow in quantum bit (qubit) count and functionality, the control and measurement system becomes a limiting factor to large scale extensibility. To tackle this challenge and keep pace with rapidly evolving classical control requirements, full control stack access is essential to system level optimization. We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software. A prototype hardware module is assembled from several commercial off-the-shelf evaluation boards and in-house developed circuit boards. Gateware and software are designed to implement basic qubit control and measurement protocols. System functionality and performance are demonstrated by performing qubit chip characterization, gate optimization, and randomized benchmarking sequences on a superconducting quantum processor operating at the Advanced Quantum Testbed at Lawrence Berkeley National Laboratory. The single-qubit and two-qubit process fidelities are measured to be 0.99800.0001 and 0.9480.004 by randomized benchmarking. With fast circuit sequence loading capability, the QubiC performs randomized compiling experiments efficiently and improves the feasibility of executing more complex algorithms.
Superconducting quantum processors have largely converged on transmon-based architectures, while alternative qubit modalities with intrinsic error protection have lacked a demonstrated path to scalable system integration. In particular, although tunable-coupler-mediated interactions have been validated for small fluxonium systems, it remains unclear whether such designs can be scaled to a multi-qubit lattice. Here, we establish a scalable fluxonium processor architecture based on a modular qubit-coupler unit cell engineered to suppress residual interactions and spectator errors in a many-qubit lattice. The system enables parallel single-qubit gate fidelities approaching 99.99% and two-qubit CZ gate fidelities around 99%. With an optimized gate duration of 32 ns, the best CZ gate fidelity reaches 99.9%. We further validate this architecture in a 22-qubit processor based on the same configuration, where parallel operations enable the deterministic generation of Greenberger-Horne-Zeilinger states involving up to 10 qubits. Together, these results demonstrate that the fluxonium-tunable-coupler unit cell composes without emergent interaction pathologies and establish fluxonium as a scalable superconducting qubit platform.