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arXiv:quant-ph/0311152 · International Journal of Quantum Information

ANALYTIC SOLUTIONS FOR QUANTUM LOGIC GATES AND MODELING PULSE ERRORS IN A QUANTUM COMPUTER WITH A HEISENBERG INTERACTION

G. P. Berman, D. I. Kamenev, V. I. Tsifrinovich

Published Jun 1, 2004• 1 citation
arXivHTMLPDF

Abstract

We analyze analytically and numerically quantum logic gates in a one-dimensional spin chain with Heisenberg interaction. Analytic solutions for basic one-qubit gates and swap gate are obtained for a quantum computer based on logical qubits. We calculated the errors caused by imperfect pulses which implement the quantum logic gates. It is numerically demonstrated that the probability error is proportional to ε4, while the phase error is proportional to ε, where ε is the characteristic deviation from the perfect pulse duration.

DOI
10.1142/s0219749904000237

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•Mar 1, 2008•0 citations
We analyze analytically and numerically quantum logic gates in a one-dimensional spin chain with Heisenberg interaction. Analytic solutions for basic one-qubit gates and swap gate are obtained for a quantum computer based on logical qubits. We calculated the errors caused by imperfect pulses which implement the quantum logic gates. It is numerically demonstrated that the probability error is proportional to ε4, while the phase error is proportional to ε, where ε is the characteristic deviation from the perfect pulse duration.
The problems of error correction in a spin quantum computer are discussed. For digital processing in the Ising and Heisenberg chains driven by a resonant electromagnetic field, the simple schemes are suggested which provide correction of errors caused by imperfect \ensuremath{\pi} pulses, and prevent the most significant errors caused by the nonresonant action of \ensuremath{\pi} pulses. The probability of error caused by the Heisenberg interaction during the action of \ensuremath{\pi} pulses is estimated. For quantum computations in spin systems a principal opportunity to correct the phase errors, based on Steane's three quantum-bits scheme, is described.
The errors caused by qubit displacements from their prescribed locations in an ensemble of spin chains are estimated analytically and calculated numerically for a quantum computer based on phosphorus donors in silicon. We show that it is possible to polarize (initialize) the nuclear spins even with displaced qubits by using controlled-NOT gates between the electron and nuclear spins of the same phosphorus atom. However, a controlled-NOT gate between the displaced electron spins is implemented with large error because of the exponential dependence of exchange interaction constant on the distance between the qubits. If quantum computation is implemented on an ensemble of many spin chains, the errors can be small if the number of chains with displaced qubits is small.
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
The construction of a solid-state quantum computer remains a coveted, yet elusive goal. Among the most promising scalable candidates are the spin-based approaches, where qubits are represented by electron spins in quantum dots, or by donor-atom nuclear or electron spins, or by combinations thereof. It has been widely assumed that one-qubit gates in these systems, which are based on single-spin addressing, suffer from severe technical difficulties, including slow speed of operation, heating, and device and materials complexity, such as g-factor engineering. For this reason a variety of approaches have been suggested to circumvent one-qubit gates, including encoding the state of a qubit into two or more spins. These approaches inevitably introduce substantial overhead. Here we show that one-qubit gates can in fact be generated using only modest and presently feasible technological requirements. Our solution uses only global magnetic fields and controllable Heisenberg exchange interactions, thus circumventing the need for single-spin addressing. We explicitly show how to build up one-qubit gates from these components using simple pulse sequences. This should substantially simplify the implemention of spin-based solid state quantum computers.
A constructive scheme has been devised to enable mapping of any quantum computation into a spintronic circuit in which the computation is encoded in a basis that is, in principle, immune to quantum decoherence. The scheme is implemented by an algorithm that utilizes multiple physical spins to encode each logical bit in such a way that collective errors affecting all the physical spins do not disturb the logical bit. The scheme is expected to be of use to experimenters working on spintronic implementations of quantum logic. Spintronic computing devices use quantum-mechanical spins (typically, electron spins) to encode logical bits. Bits thus encoded (denoted qubits) are potentially susceptible to errors caused by noise and decoherence. The traditional model of quantum computation is based partly on the assumption that each qubit is implemented by use of a single two-state quantum system, such as an electron or other spin-1.2 particle. It can be surprisingly difficult to achieve certain gate operations . most notably, those of arbitrary 1-qubit gates . in spintronic hardware according to this model. However, ironically, certain 2-qubit interactions (in particular, spin-spin exchange interactions) can be achieved relatively easily in spintronic hardware. Therefore, it would be fortunate if it were possible to implement any 1-qubit gate by use of a spin-spin exchange interaction. While such a direct representation is not possible, it is possible to achieve an arbitrary 1-qubit gate indirectly by means of a sequence of four spin-spin exchange interactions, which could be implemented by use of four exchange gates. Accordingly, the present scheme provides for mapping any 1-qubit gate in the logical basis into an equivalent sequence of at most four spin-spin exchange interactions in the physical (encoded) basis. The complexity of the mathematical derivation of the scheme from basic quantum principles precludes a description within this article; it must suffice to report that the derivation provides explicit constructions for finding the exchange couplings in the physical basis needed to implement any arbitrary 1-qubit gate. These constructions lead to spintronic encodings of quantum logic that are more efficient than those of a previously published scheme that utilizes a universal but fixed set of gates.