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Bulletin of the American Physical Society

VCSEL-based CPT atomic clock: Understanding the magic modulation index

Michael Crescimanno, Irina V. Novikova, Yanhong Xiao, David F. Phillips, R. L. Walsworth

Published Apr 1, 2006• 0 citations
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We propose a model to reduce the influence that the light-shift induced frequency drift has on the long-term stability of coherent population trapping (CPT)-based low-power atomic clocks. We experimentally validated the proposed model using the chip-scale atomic clock architecture. The model considers both the drift of the dc-bias current to compensate for the wavelength aging of the vertical-cavity surface-emitting laser (VCSEL) and the variation in the modulation index of the light field generated by the VCSEL. We investigated the dc-bias-current-dependency of the frequency drift in an atomic clock module both theoretically and experimentally, confirming that the frequency drift can change as a function of the VCSEL basic parameters. When the atomic clock module was operated over a period of five months at the dc-bias current affording a zero-crossing of the clock frequency drift, the Allan standard deviation and clock frequency drift for long-term stability were 8.0×10−12 for averaging times of 4×106 s and 2.4×10−13/day, respectively. Our approach is promising to improve the long-term stability of CPT-based low-power atomic clocks.

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Atomic clocks for compact satellite missions have limitations on size, weight, and power (SWaP), while requiring ever greater levels of frequency stability and accuracy. To aid in the development of next-generation low SWaP Coherent Population Trapping (CPT) clocks, we are developing a CubeSat Atomic Clock Testbed (CuSACT). This testbed will give us the capability to vary single aspects of CPT-clock design while keeping all others constant. In this presentation, we will provide an overview of CuSACT, and discuss our preliminary results comparing direct injection-current modulation of a VCSEL with electro-optic phase modulation of the VCSEL.

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Chip-scale atomic clocks are critical for applications requiring compact, energy-efficient, and highly stable timing, such as GPS receivers and communication systems. Coherent population trapping (CPT)-based atomic clocks, which commonly use vertical-cavity surface-emitting lasers (VCSELs), have enabled significant miniaturization. However, their precision is limited by the broad linewidth of VCSELs. Alternative laser technologies, such as distributed Bragg reflector lasers, distributed feedback lasers, and external cavity diode lasers (ECDLs), offer potential improvements but face challenges in achieving compact size and adequate modulation bandwidth. This study presents a 795 nm chip-ECDL with a direct modulation bandwidth up to 4 GHz, specifically designed for CPT chip-scale atomic clocks. Based on the chip-ECDL, a CPT atomic clock with a compact volume of 19.4 ml and power consumption of 1.5 W has been developed. Under identical operating conditions, the CPT signal produced by the chip-ECDL exhibits a 34% reduction in linewidth and a 1.14-fold increase in contrast compared to a VCSEL-based clock. Demonstrating short-term stability better than 5×10−11τ−1/2(1 s<τ<2000 s) and reaching a best stability of 6.6×10−13 at 2000 s, this work represents the application of an ECDL in a CPT chip-scale clock, advancing the development of next-generation, high-performance chip-scale atomic clocks.

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Optics & Laser Technology•Jun 22, 2019•26 citations
We propose a model to reduce the influence that the light-shift induced frequency drift has on the long-term stability of coherent population trapping (CPT)-based low-power atomic clocks. We experimentally validated the proposed model using the chip-scale atomic clock architecture. The model considers both the drift of the dc-bias current to compensate for the wavelength aging of the vertical-cavity surface-emitting laser (VCSEL) and the variation in the modulation index of the light field generated by the VCSEL. We investigated the dc-bias-current-dependency of the frequency drift in an atomic clock module both theoretically and experimentally, confirming that the frequency drift can change as a function of the VCSEL basic parameters. When the atomic clock module was operated over a period of five months at the dc-bias current affording a zero-crossing of the clock frequency drift, the Allan standard deviation and clock frequency drift for long-term stability were 8.0×10−12 for averaging times of 4×106 s and 2.4×10−13/day, respectively. Our approach is promising to improve the long-term stability of CPT-based low-power atomic clocks.
Atomic clocks for compact satellite missions have limitations on size, weight, and power (SWaP), while requiring ever greater levels of frequency stability and accuracy. To aid in the development of next-generation low SWaP Coherent Population Trapping (CPT) clocks, we are developing a CubeSat Atomic Clock Testbed (CuSACT). This testbed will give us the capability to vary single aspects of CPT-clock design while keeping all others constant. In this presentation, we will provide an overview of CuSACT, and discuss our preliminary results comparing direct injection-current modulation of a VCSEL with electro-optic phase modulation of the VCSEL.
Chip-scale atomic clocks are critical for applications requiring compact, energy-efficient, and highly stable timing, such as GPS receivers and communication systems. Coherent population trapping (CPT)-based atomic clocks, which commonly use vertical-cavity surface-emitting lasers (VCSELs), have enabled significant miniaturization. However, their precision is limited by the broad linewidth of VCSELs. Alternative laser technologies, such as distributed Bragg reflector lasers, distributed feedback lasers, and external cavity diode lasers (ECDLs), offer potential improvements but face challenges in achieving compact size and adequate modulation bandwidth. This study presents a 795 nm chip-ECDL with a direct modulation bandwidth up to 4 GHz, specifically designed for CPT chip-scale atomic clocks. Based on the chip-ECDL, a CPT atomic clock with a compact volume of 19.4 ml and power consumption of 1.5 W has been developed. Under identical operating conditions, the CPT signal produced by the chip-ECDL exhibits a 34% reduction in linewidth and a 1.14-fold increase in contrast compared to a VCSEL-based clock. Demonstrating short-term stability better than 5×10−11τ−1/2(1 s<τ<2000 s) and reaching a best stability of 6.6×10−13 at 2000 s, this work represents the application of an ECDL in a CPT chip-scale clock, advancing the development of next-generation, high-performance chip-scale atomic clocks.