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Evaluation Data to "From QCCD Trapped-Ion Hardware to Quantum Compilers: Capabilities, Architectures, and Compilation"

L. Schmid, Josef Eisinger, Daniel Schönberger, Christian D. Marciniak, Janine Hilder, Ulrich Poschinger, Robert Wille, Ferdinand Schmidt‐Kaler

Published Oct 20, 2026• 0 citations
Publisher

Abstract

Data and plotting scripts for the case studies in “From QCCD Trapped-Ion Hardware to Quantum Compilers: Capabilities, Architectures, and Compilation”. Two circuits, randomly generated interaction layers and a logical teleportation circuit on the [[7,1,3]] Steane code, were compiled onto a 1D linear segmented register and onto a 2D grid with processing zones outside the memory region. The archive holds the resulting routing costs as CSV, the teleportation circuit as OpenQASM 2.0, and the scripts that draw the paper’s two case-study figures from them. uv run scripts/plot_scaling.py and uv run scripts/plot_teleportation.py regenerate both figures.

DOI
10.5281/zenodo.23502074

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Data and plotting scripts for the case studies in “From QCCD Trapped-Ion Hardware to Quantum Compilers: Capabilities, Architectures, and Compilation”. Two circuits, randomly generated interaction layers and a logical teleportation circuit on the [[7,1,3]] Steane code, were compiled onto a 1D linear segmented register and onto a 2D grid with processing zones outside the memory region. The archive holds the resulting routing costs as CSV, the teleportation circuit as OpenQASM 2.0, and the scripts that draw the paper’s two case-study figures from them. uv run scripts/plot_scaling.py and uv run scripts/plot_teleportation.py regenerate both figures.
Shuttling-based trapped-ion quantum computers (QCCD) rank among the most mature hardware platforms. Existing and envisaged devices exhibit architectural differences in terms of register layout and connectivity. Platform-specific compilers are required to translate quantum circuits into resource-optimized hardware-level command chains. Hardware platforms and compiler software stacks are mostly developed independently of one another by different research communities. This work aims to bridge these communities by abstracting QCCD architectures and native operations, enabling computer scientists to address compilation problems using generic methods without requiring a deep background in the physical operating principles of the platform. The resulting design space is organized into a small set of architectural archetypes, each posing its own compilation problem. We then select and apply compilation methods to one- and two-dimensional QCCD architectures, finding that the routing overhead scales approximately cubically with the number of qubits for the one-dimensional architecture and approximately quadratically for the two-dimensional one. Extending this to compilation with a quantum error-correction layer reveals additional differences and similarities between the physical and logical levels. We conclude that co-design is a requirement rather than an option, and this work provides the vocabulary, archetypes, and compilation abstraction it needs.
Trapped-ion quantum computers hold significant promise as platforms for high-quality qubits and reliable quantum computation. The Quantum Charge Coupled Device (QCCD) architecture shows potential in enabling scalable trapped-ion quantum computers through its modular design. Within QCCD devices, ions can be shuttled throughout the trap, which is divided into different dedicated zones, e.g. a memory zone for storage and a processing zone for actual computation. While the modular approach shows promise, designing a large-scale QCCD device remains challenging due to the numerous possibilities involved in designing the precise architecture of the hardware. In this work, we propose leveraging existing compilers to evaluate design choices in the development of QCCD architectures. Rather than compiling specifically for a single device, we use the compiler to explore and evaluate the execution of representative quantum circuits on various architectures. This allows for a fast assessment of different design choices, considering individual requirements and physical limitations. To validate the feasibility of this idea, we conducted a study focusing on key design decisions, including system size, junction density, processing zone positioning, and the benefits of SWAP operations within the memory zone. Based on these results, we are able to provide first recommendations and insights for the design of future QCCD architectures.
Shuttle-based trapped ion quantum processors typically employ a one-dimensional (1D) linear architecture to transport ion-qubits between one ore more laser interaction zones where the quantum gates are implemented, along with several qubit register storage segments. The two-dimensional (2D) quantum CCD architecture employs also T- or X-junctions for an improved scaling and efficiency. Here, we explore the shuttling layer in the compilation of quantum algorithm typical building blocks in such architecture. To weight the effort of linear shuttle and junction shuttle, we introduce individual cost functions for each operation. This allows comparing the total cost for quantum circuit building blocks such as the QFT, Carry, Adder, Shift, and Comparator circuits. We study their scaling properties with increased qubit numbers. At equivalent transport cost for junction and linear shuttling, we show that 2D architectures outperform the 1D linear trap with the ratio improving as the number of ions increases. Finally, we discuss the use of cells, such that the entire processor is constructed from a 2D array of such interconnected cells. The work aims to optimize quantum processor architectures, implementing a co-design that fits to the specific task and scaling up in a shuttle-efficient way.