As quantum computing has progressed toward fault-tolerant implementations, quantum error correction (QEC) for quantum hardware and software has become a dominant concern. While conventional QEC measurements, such as qubit overhead, code distance, and error thresholds, quantify physical resource costs, they do not capture the software-level functionality introduced by error detection, correction, and fault-tolerant gate protocols. This study investigated the QEC contribution to the functional size of quantum software and demonstrated that this contribution can be systematically measured using the COSMIC Functional Size Measurement method. A gate-level sizing approach, known as Gates’ Occurrences, was used to quantify functional user requirements (FUR) associated with QEC processes, including logical encoding, syndrome extraction, and recovery operations. A prototype measurement tool, implemented in Qiskit (Version 0.7.2), enables the automated calculation of COSMIC Function Points (CFP) from annotated circuit representations. Case studies involving Bell state preparation, Grover’s search algorithm, and 15-to-1 magic state distillation revealed that QEC-related functionality can account for 70–85% of the total functional size, even under simplified encoding assumptions. The results underscore the importance of QEC for the functional size of quantum software. These findings offer a reproducible foundation for functional sizing and future fault-tolerant quantum applications.
As quantum computing has progressed toward fault-tolerant implementations, quantum error correction (QEC) for quantum hardware and software has become a dominant concern. While conventional QEC measurements, such as qubit overhead, code distance, and error thresholds, quantify physical resource costs, they do not capture the software-level functionality introduced by error detection, correction, and fault-tolerant gate protocols. This study investigated the QEC contribution to the functional size of quantum software and demonstrated that this contribution can be systematically measured using the COSMIC Functional Size Measurement method. A gate-level sizing approach, known as Gates’ Occurrences, was used to quantify functional user requirements (FUR) associated with QEC processes, including logical encoding, syndrome extraction, and recovery operations. A prototype measurement tool, implemented in Qiskit (Version 0.7.2), enables the automated calculation of COSMIC Function Points (CFP) from annotated circuit representations. Case studies involving Bell state preparation, Grover’s search algorithm, and 15-to-1 magic state distillation revealed that QEC-related functionality can account for 70–85% of the total functional size, even under simplified encoding assumptions. The results underscore the importance of QEC for the functional size of quantum software. These findings offer a reproducible foundation for functional sizing and future fault-tolerant quantum applications.
Surface-code quantum error correction (QEC) is pivotal for fault-tolerant quantum computing, but its energy efficiency remains underexplored. This work derives a practical lower bound on the energy cost per logical-qubit operation, accounting for gate-fidelity decay's impact on code distance and physical-qubit overhead. By modeling the energy consumption of gate operations and error correction, we express the total cost as $ E = (E_g N_g + E_c N_c)/N_l $, where $ E_g $, $ E_c $, $ N_g $, $ N_c $, and $ N_l $ represent gate and physical-qubit energy costs, gate counts, physical-qubit counts, and logical qubit counts, respectively. Gate-fidelity decay increases the required code distance $ d $, scaling $ N_c $ and thus $ E $. We propose normalizing computational cost in joules per logical-qubit operation (JPCUB), isolating logical work from error-correction overhead. Quantitative predictions for $ E_g $, $ E_c $, and $ N_c $ remain [to verify], but the functional dependence on $ d $ and gate fidelities is established. This framework informs energy-efficient QEC design and benchmarks. ## 1. Introduction Surface codes enable fault-tolerant quantum computation by encoding logical qubits in a 2D lattice of physical qubits, correcting errors through syndrome measurements. However, the energy cost per logical operation—critical for scalability—remains poorly quantified. While theoretical foundations exist (Raussendorf & Terhal, 2006; Kitaev, 2003), prior work focuses on error-correction thresholds rather than energy efficiency. Here, we address this gap by deriving a lower bound on energy cost, considering how gate-fidelity decay necessitates larger code distances $ d $, increasing physical-qubit overhead $ N_c $. This analysis connects to the joules-per-compute (JPCUB) benchmark, advocating for energy normalization per logical qubit to disentangle computational work from error-correction costs. ## 2. Background Surface codes encode logical qubits using a 2D grid of
Fault-tolerant quantum error correction (QEC) networks are studied by a combination of numerical and approximate analytical treatments. The probability of failure of the recovery operation is calculated for a variety of Calderbank-Shor-Steane codes, including large block codes and concatenated codes. Recent insights into the syndrome extraction process, which render the whole process more efficient and more noise tolerant, are incorporated. The average number of recoveries that can be completed without failure is thus estimated as a function of various parameters. The main parameters are the gate $\ensuremath{\gamma}$ and memory $\ensuremath{\epsilon}$ failure rates, the physical scale-up of the computer size, and the time tm required for measurements and classical processing. The achievable computation size is given as a surface in parameter space. This indicates the noise threshold as well as other information. It is found that concatenated codes based on the [[23,1,7]] Golay code give higher thresholds than those based on the [[7,1,3]] Hamming code under most conditions. The threshold gate noise ${\ensuremath{\gamma}}_{0}$ is a function of $\ensuremath{\epsilon}/\ensuremath{\gamma}$ and tm; example values are ${\ensuremath{\epsilon}/\ensuremath{\gamma}{,t}_{m},{\ensuremath{\gamma}}_{0}}={{1,1,10}^{\ensuremath{-}3}},$ ${0.01,1,3\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}3}},$ ${{1,100,10}^{\ensuremath{-}4}},$ ${0.01,100,2\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}3}},$ assuming zero cost for information transport. This represents an order of magnitude increase in tolerated memory noise, compared with previous calculations, which is made possible by recent insights into the fault-tolerant QEC process.
Quantum error correction (QEC) represents a critical enabler for fault-tolerant quantum computing, protecting fragile quantum states from decoherence and operational errors. This paper provides a comprehensive analysis of leading quantum error correction schemes, focusing on surface codes and topological codes within the context of Noisy Intermediate-Scale Quantum (NISQ) era processors. We examine the theoretical foundations of stabilizer codes, compare surface code implementations with code distances ranging from d=3 to d=17, and analyze topological codes including toric codes and color codes. Our investigation encompasses syndrome extraction circuits, logical qubit encoding strategies, and threshold analysis for contemporary quantum hardware platforms. Performance metrics reveal that surface codes achieve error thresholds of approximately 1% with realistic noise models, while topological codes offer architectural advantages for specific qubit connectivity constraints. We discuss implementation challenges on current NISQ processors including IBM Quantum, Google Sycamore, and IonQ systems, addressing qubit overhead, gate fidelity requirements, and decoding algorithms. This analysis provides insights for selecting appropriate error correction schemes based on application requirements and hardware capabilities.
Quantum error correction protects fragile quantum information by encoding it into a larger quantum system. These extra degrees of freedom enable the detection and correction of errors, but also increase the operational complexity of the encoded logical qubit. Fault-tolerant circuits contain the spread of errors while operating the logical qubit, and are essential for realizing error suppression in practice. While fault-tolerant design works in principle, it has not previously been demonstrated in an error-corrected physical system with native noise characteristics. In this work, we experimentally demonstrate fault-tolerant preparation, measurement, rotation, and stabilizer measurement of a Bacon-Shor logical qubit using 13 trapped ion qubits. When we compare these fault-tolerant protocols to non-fault tolerant protocols, we see significant reductions in the error rates of the logical primitives in the presence of noise. The result of fault-tolerant design is an average state preparation and measurement error of 0.6% and a Clifford gate error of 0.3% after error correction. Additionally, we prepare magic states with fidelities exceeding the distillation threshold, demonstrating all of the key single-qubit ingredients required for universal fault-tolerant operation. These results demonstrate that fault-tolerant circuits enable highly accurate logical primitives in current quantum systems. With improved two-qubit gates and the use of intermediate measurements, a stabilized logical qubit can be achieved.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.