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International Journal for Research in Science Engineering & Technology

DESIGN AND IMPLEMENTATION OF ERSFQ BASED GDI TECHNIQUE USING TANNER

Abirami G, Punithavathy Mohan

Published Oct 30, 2018• 0 citations
Publisher

Abstract

Rapid Single Flux Quantum (RSFQ) is a digital electronic technology that uses superconducting devices to process the digital signals. The information is stored inthe form of magnetic flux quanta, in RFSQ logic. Resistor-free approach to dc biasing of RSFQ logical circuits are known as Energy-efficient Rapid Single FluxQuantum (ERSFQ) that does not use bias resistors. The ERSFQ logic is to eliminate the static power loss of RSFQ by replacing bias resistors with set of inductors and current-limiting Josephson junction. Traditionally, the ERSFQ logical circuit is designed in this paper. In the ERSFQ architecture, numbers of half adders are used to design this structure. The main disadvantage of ERFSQ structure, the number of transistor count is increased. In order to reduce this problem, ERFSQ based GDI (Gate Diffusion Input) technique is proposed in this paper. The schematic circuit of proposed ERSFQ based GDI technique is designed by using Tanner EDA tool.

DOI
10.5281/ijrset.v3i3.91

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Rapid Single Flux Quantum (RSFQ) is a digital electronic technology that uses superconducting devices to process the digital signals. The information is stored inthe form of magnetic flux quanta, in RFSQ logic. Resistor-free approach to dc biasing of RSFQ logical circuits are known as Energy-efficient Rapid Single FluxQuantum (ERSFQ) that does not use bias resistors. The ERSFQ logic is to eliminate the static power loss of RSFQ by replacing bias resistors with set of inductors and current-limiting Josephson junction. Traditionally, the ERSFQ logical circuit is designed in this paper. In the ERSFQ architecture, numbers of half adders are used to design this structure. The main disadvantage of ERFSQ structure, the number of transistor count is increased. In order to reduce this problem, ERFSQ based GDI (Gate Diffusion Input) technique is proposed in this paper. The schematic circuit of proposed ERSFQ based GDI technique is designed by using Tanner EDA tool.
Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.
Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.
Abstract As a member of the superconducting integrated circuit family, energy-efficient rapid single flux quantum (ERSFQ) circuit combines low-power consumption with high frequency, showing promise for application in high-energy efficient neuromorphic computing and traditional high-performance computing. Previous studies have demonstrated that there are typically two energy dissipation states in working ERSFQ circuits: energy-efficient SFQ state (E-state) and resistive-biased SFQ state (R-state). These states occur at different biasing current ranges, and the sum of the bias margin of these two states is close to the margin of rapid single flux quantum (RSFQ) circuits of the same design. For ultra-low-power applications, the bias current margin of the R-state must be excluded, leading to a substantially narrower bias margin in ERSFQ circuits than in their RSFQ counterparts. In our previous research, we proposed the feeding pulse method to increase the bias current margin by extending the lower boundary of the E-state through the injection of feeding pulses into the feeding Josephson transmission line (FJTL). In this study, we further investigated the current distribution mechanism in ERSFQ circuits and, based on this, proposed a method of optimizing design of the FJTL to redirect excess current to the FJTL, so as to expand the upper boundary of the E-state’s bias current margin. We tested an ERSFQ 8-bit shift register of the ERSFQ by applying methods proposed in this work together with the feeding pulses method proposed before. The results demonstrated that the bias current margin of the E-state expanded from (94%, 98%) to (56%, 116%), corresponding to a 14-times increase, with both the lower and upper boundary successfully extended. Our research addresses the issue of limited current bias margin in ERSFQ circuits during actual operation, providing a more robust ERSFQ technology for future applications in neural networks and high-performance computing.
We designed and tested low-power digital gates based on the energy-efficient rapid single flux quantum (ERSFQ) and on the reversible nSQUID logic. The ERSFQ circuit consists of a series of 13 toggle flip-flops (TFFs), where the bias resistors are replaced by inductors which generate no energy dissipation in the static mode, resulting in a power consumption orders of magnitude below that of traditional RSFQ circuits during operation. The ERSFQ circuits were fabricated with HYPRES' standard 4.5-kA/cm2process and tested up to 20 GHz. The RF input level was about -25 dBm 50 Ω matched, and the output level was 400 μVpp. The nSQUID ring with “NOT” gates was fabricated with HYPRES' standard 1-kA/cm2process. The “0” and “1” input logic signals were realized injecting ±5 mA of current in a superconductive coil, obtaining 6 μVpp of amplitude as output signal. The test was performed at low frequency in order to verify the functionality and the ultralow power consumption.
We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm2process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm2process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm2planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm2process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.