Image processing hardware should be able to perform repeated pixel-level operations with minimal overhead by designing compact arithmetic-logic circuitry. A compact reversible logic architecture offers a promising alternative to conventional architectures in image-processing applications due to its high throughput and energy efficiency. Additionally, reversible arithmetic circuits minimize resource utilization while preserving computational functionality, providing a scalable foundation for quantum-inspired computing platforms. The aim of this paper is to develop a low-quantum-cost reversible arithmetic-logic circuit that could serve as the basis of quantum-inspired image processing systems in the future. The proposed design incorporates only three gates, 16 selector-controlled outputs, four garbage outputs, and three constant inputs. The proposed design uses three composite reversible blocks. Its resource requirements are compared with earlier reversible ALU designs using the reported quantum costs, gate counts, garbage outputs, and constant inputs. The design does not propose a complete image processor, but rather a contribution at the circuit level.
Image processing hardware should be able to perform repeated pixel-level operations with minimal overhead by designing compact arithmetic-logic circuitry. A compact reversible logic architecture offers a promising alternative to conventional architectures in image-processing applications due to its high throughput and energy efficiency. Additionally, reversible arithmetic circuits minimize resource utilization while preserving computational functionality, providing a scalable foundation for quantum-inspired computing platforms. The aim of this paper is to develop a low-quantum-cost reversible arithmetic-logic circuit that could serve as the basis of quantum-inspired image processing systems in the future. The proposed design incorporates only three gates, 16 selector-controlled outputs, four garbage outputs, and three constant inputs. The proposed design uses three composite reversible blocks. Its resource requirements are compared with earlier reversible ALU designs using the reported quantum costs, gate counts, garbage outputs, and constant inputs. The design does not propose a complete image processor, but rather a contribution at the circuit level.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.
Reversible logic provides a foundation for nextgeneration computing systems, particularly in quantum and emerging nanotechnology-based architectures. Unlike conventional logic, reversible gates preserve information and support backward computation, making them crucial for designing quantum circuits. This paper introduces a reversible Arithmetic and Logic Unit (ALU) that performs eight fundamental operations-AND, OR, NOT, XOR, addition, subtraction, increment, and decrement-using Fredkin, Peres, TR, and modified Fredkin gates. A dedicated control unit manages operation selection, ensuring functional flexibility and circuit efficiency. The proposed design achieves significant improvements by minimizing ancilla inputs, quantum cost and garbage outputs, resulting in a total quantum cost of 71 and contains 16 reversible gates and 14 garbage outputs. The architecture was modeled and verified using Xilinx Vivado HLS and ISE 14.7, and implemented on the Nexys A7 (Artix-7) FPGA platform. Comparative analysis demonstrates better efficiency than existing reversible ALU designs, establishing the proposed circuit as a strong candidate for quantum computing and other advanced computing paradigms.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
Reversible computing is an emerging field of research and has made remarkable progress. Owing to the reduced energy dissipation in reversible circuits, a lot of research has been done on the design of reversible circuits. In reversible logic circuit designs, along with primary inputs, few constant inputs (Ancilla Inputs) are used to realize required reversible functions. In addition to this, few unused or extra output bits are generated; these bits are named as Garbage Output bits. A challenge in the reversible computation is to use minimum Ancilla Inputs and generate zero Garbage Outputs. In this work, we present designs for addition, subtraction, and addition or subtraction operations. The designs are primarily optimized to achieve zero Garbage Outputs and minimum Ancilla Inputs. In addition, these proposed arithmetic circuits are designed for best Gate Count and Quantum Cost values compared to the existing counterparts.
Reversible logic technology has the most promising role in quantum computing. With the evolution of high-performance computing devices, future processors are focusing on quantum technology for their development and fabrication. This work focuses on the development of a novel digital processor with memory via parity-preserving reversible logic gates and quantum cellular automaton (QCA). The design and realization of the integral components of the digital processor have been performed with reversible KMD gates. The processor’s main modules include the ALU, multipliers, floating-point division unit, control unit, and memory unit. It has a control unit to monitor and control the operation of the processor. The QCA design of individual modules of the developed processor is carried out with appropriate multilayer wire crossing. The performances of the individual models of the processor are compared and analyzed with those of existing designs. The reversible processor has 891 quantum costs, 141 constant inputs, and 188 garbage outputs; it needs 120 reversible gates and 1397 total costs. The results show that the developed processor modules are better than the existing modules, as the appropriate use of reversible logic gates for modern-day high-performance, economical and low-power-consumption processors.
Quantum computation is modeled by quantum circuits. All the quantum operations are reversible so the quantum circuits can be built using reversible logic gates. Reversible computing is the emerging technology, its major role is in the field of quantum computing, optical computing, and design of low power nanocircuits. The most frequently used computational unit for digital signal processing and multimedia applications is multiplier. To compute square of an operand, regular multipliers are used in general. This paper proposes a dedicated quantum circuit for computing square of an operand efficiently compared to the existing multipliers in the literature. The squaring unit is mathematically modeled and its metrics quantum cost, garbage outputs and ancilla input, gate count are calculated. We compared the proposed design with the existing multipliers to compute square and found that proposed square unit is efficient in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The proposed reversible square circuit has 63% to 85% improvement of quantum cost, garbage outputs, ancilla inputs and gate count over existing reversible multiplier circuits.