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TETRIS-Q: Tiling-based Effective Transient-fault Reduction and Parallelism Optimizations for Quantum Circuit Mapping

Rowan Brad Quni-Gudzinas

Published Sep 8, 2026• 0 citations
Publisher

Abstract

Quantum circuit mapping on Noisy Intermediate-Scale Quantum (NISQ) devices must satisfy physical connectivity constraints while minimizing both SWAP overhead and exposure to transient faults like decoherence. Existing compilers typically optimize qubit routing and noise-aware placement independently, failing to jointly exploit spatial structure to reduce both SWAP depth and idle-time-induced decoherence. We introduce TETRIS-Q, a mapping framework that partitions the physical qubit topology into local rectangular tiles. This tiling abstraction enables a unified strategy: tile-local mapping minimizes idle qubit lifetimes, while cross-tile parallel scheduling maximizes concurrent two-qubit gate execution. By treating transient-fault probability as a function of idle duration and gate ordering, rather than just circuit depth, TETRIS-Q jointly penalizes SWAP count and cumulative idle time. On grid-heavy architectures, we project a 10–30% reduction in SWAP count [to verify] and measurable fidelity improvements over routing-only baselines [to verify]. This approach demonstrates that spatial tiling offers a robust paradigm for high-fidelity NISQ compilation. ## 1. Introduction Compiling quantum algorithms for Noisy Intermediate-Scale Quantum (NISQ) hardware requires mapping logical qubits onto physical qubits with limited connectivity. To execute gates between non-adjacent physical qubits, compilers insert SWAP gates—operations that exchange qubit states—to route interacting qubits into adjacency. While SWAP gates introduce additional circuit depth and gate errors, they also indirectly increase exposure to transient faults (decoherence and relaxation, characterized by T1 and T2 timescales) by extending the duration that idle qubits wait for dependent operations. Existing quantum compilers generally treat routing minimization and noise-aware placement as separate optimization passes. However, this independent optimization misses opportunities to exploit the spatial locali

DOI
10.5281/zenodo.22658272

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Quantum circuit mapping on Noisy Intermediate-Scale Quantum (NISQ) devices must satisfy physical connectivity constraints while minimizing both SWAP overhead and exposure to transient faults like decoherence. Existing compilers typically optimize qubit routing and noise-aware placement independently, failing to jointly exploit spatial structure to reduce both SWAP depth and idle-time-induced decoherence. We introduce TETRIS-Q, a mapping framework that partitions the physical qubit topology into local rectangular tiles. This tiling abstraction enables a unified strategy: tile-local mapping minimizes idle qubit lifetimes, while cross-tile parallel scheduling maximizes concurrent two-qubit gate execution. By treating transient-fault probability as a function of idle duration and gate ordering, rather than just circuit depth, TETRIS-Q jointly penalizes SWAP count and cumulative idle time. On grid-heavy architectures, we project a 10–30% reduction in SWAP count [to verify] and measurable fidelity improvements over routing-only baselines [to verify]. This approach demonstrates that spatial tiling offers a robust paradigm for high-fidelity NISQ compilation. ## 1. Introduction Compiling quantum algorithms for Noisy Intermediate-Scale Quantum (NISQ) hardware requires mapping logical qubits onto physical qubits with limited connectivity. To execute gates between non-adjacent physical qubits, compilers insert SWAP gates—operations that exchange qubit states—to route interacting qubits into adjacency. While SWAP gates introduce additional circuit depth and gate errors, they also indirectly increase exposure to transient faults (decoherence and relaxation, characterized by T1 and T2 timescales) by extending the duration that idle qubits wait for dependent operations. Existing quantum compilers generally treat routing minimization and noise-aware placement as separate optimization passes. However, this independent optimization misses opportunities to exploit the spatial locali
Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit-mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T_2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present transverse relaxation time–aware qubit-mapping (TRAM), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.29% in fidelity, reduces gate count by 11.47%, and shortens circuit depth by 12.29%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.
Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present TRAM (Transverse Relaxation Time-Aware Qubit Mapping), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.59% in fidelity, reduces gate count by 11.49%, and shortens circuit depth by 12.28%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.
We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
This work presents a routing-aware pruning strategy for quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) devices. We propose a method to remove parametric controlled rotations whose small rotation angles do not justify the routing overhead required for their implementation. By selectively pruning such gates, the method mitigates fidelity loss arising from additional SWAP operations introduced during compilation. Our approach evaluates whether executing a gate leads to greater fidelity loss than omitting it. Simulations on benchmark circuits with realistic noise models show that the method reduces two-qubit gate counts (up to 48.6%) while improving final state fidelity (up to 47.7%), especially for larger circuits where routing costs dominate.
The struggle of the hour in quantum computing research is achieving effective suppression of the error mechanisms induced by the interaction of external radiation with superconducting quantum devices. Despite the rapid advancements in quantum error correction (QEC) of recent years, radiation-induced faults are yet to be fully addressed. These events are known to be the cause of simultaneous correlated defects in qubits that lie onto a single substrate, ultimately jeopardising QEC code effectiveness. In this paper, we propose to selectively combine substrate-level phonon barriers and QEC interleaving via a planar-mesh tiling algorithm, TETRIS-Q, reaching efficient and effective suppression of radiation events. Our cross-layer solution comes at no extra cost in terms of QEC code execution or decoding time. We model and simulate radiation-induced transient faults over a plethora of barrier and QEC interleaving configurations. Through more than 51 million quantum circuit simulations, we show peak logical error reductions of more than 99.8%99.8 \%99.8%, together with an 80%80\%80% reduction of the observable transient duration with permeable barriers. We find that sparser tiling can reach comparable performance to single qubit tiling, prompting cost reductions of upwards of 87%87 \%87% in barrier tracing. By leveraging independent QEC code interleaving, we measure up to one order of magnitude average logical error rate reductions without the use of permeable barriers, and up to three orders of magnitude with the joint usage of barriers.