Current joules-per-compute (JPCUB) benchmarks normalize energy consumption per physical gate, conflating logical operations with error-correction overhead. This obscures trade-offs between qubit connectivity, gate fidelity, and fault-tolerant design, hindering equitable comparisons of quantum processors. We propose a revised JPCUB metric that normalizes energy use per logical-qubit operation, isolating logical computation from error-correction infrastructure. The protocol involves executing standardized logical circuits (e.g., Clifford operations) on surface-code qubits, measuring total energy, and decomposing it into logical gate costs and error-correction overhead. By standardizing benchmark circuits and energy measurement techniques, this approach enables reproducible evaluations of quantum architectures. Simulations suggest [to verify] a 2–5× reduction in JPCUB for fault-tolerant systems compared to uncorrected benchmarks, highlighting the interplay between logical efficiency and error-correction demands. ## 1. Introduction Quantum computing architectures face escalating energy demands as they scale, necessitating rigorous metrics to evaluate efficiency. The existing JPCUB benchmark, which quantifies energy per physical gate [arXiv:2006.07065], fails to distinguish between the energy required for logical operations and that consumed by error correction. Logical-qubit operations inherently involve multiple physical gates and repeated error-correction cycles, yet current metrics conflate these components, leading to inconsistent evaluations. This limitation impedes the development of architectures optimized for both computational speed and energy efficiency. Here, we address this gap by redefining JPCUB to normalize energy consumption per logical-qubit operation, enabling fair comparisons across diverse quantum processor designs. ## 2. Background Quantum processors execute logical operations through sequences of physical gates, with error correction ensuri
Current joules-per-compute (JPCUB) benchmarks normalize energy consumption per physical gate, conflating logical operations with error-correction overhead. This obscures trade-offs between qubit connectivity, gate fidelity, and fault-tolerant design, hindering equitable comparisons of quantum processors. We propose a revised JPCUB metric that normalizes energy use per logical-qubit operation, isolating logical computation from error-correction infrastructure. The protocol involves executing standardized logical circuits (e.g., Clifford operations) on surface-code qubits, measuring total energy, and decomposing it into logical gate costs and error-correction overhead. By standardizing benchmark circuits and energy measurement techniques, this approach enables reproducible evaluations of quantum architectures. Simulations suggest [to verify] a 2–5× reduction in JPCUB for fault-tolerant systems compared to uncorrected benchmarks, highlighting the interplay between logical efficiency and error-correction demands. ## 1. Introduction Quantum computing architectures face escalating energy demands as they scale, necessitating rigorous metrics to evaluate efficiency. The existing JPCUB benchmark, which quantifies energy per physical gate [arXiv:2006.07065], fails to distinguish between the energy required for logical operations and that consumed by error correction. Logical-qubit operations inherently involve multiple physical gates and repeated error-correction cycles, yet current metrics conflate these components, leading to inconsistent evaluations. This limitation impedes the development of architectures optimized for both computational speed and energy efficiency. Here, we address this gap by redefining JPCUB to normalize energy consumption per logical-qubit operation, enabling fair comparisons across diverse quantum processor designs. ## 2. Background Quantum processors execute logical operations through sequences of physical gates, with error correction ensuri
Surface-code quantum error correction (QEC) is pivotal for fault-tolerant quantum computing, but its energy efficiency remains underexplored. This work derives a practical lower bound on the energy cost per logical-qubit operation, accounting for gate-fidelity decay's impact on code distance and physical-qubit overhead. By modeling the energy consumption of gate operations and error correction, we express the total cost as $ E = (E_g N_g + E_c N_c)/N_l $, where $ E_g $, $ E_c $, $ N_g $, $ N_c $, and $ N_l $ represent gate and physical-qubit energy costs, gate counts, physical-qubit counts, and logical qubit counts, respectively. Gate-fidelity decay increases the required code distance $ d $, scaling $ N_c $ and thus $ E $. We propose normalizing computational cost in joules per logical-qubit operation (JPCUB), isolating logical work from error-correction overhead. Quantitative predictions for $ E_g $, $ E_c $, and $ N_c $ remain [to verify], but the functional dependence on $ d $ and gate fidelities is established. This framework informs energy-efficient QEC design and benchmarks. ## 1. Introduction Surface codes enable fault-tolerant quantum computation by encoding logical qubits in a 2D lattice of physical qubits, correcting errors through syndrome measurements. However, the energy cost per logical operation—critical for scalability—remains poorly quantified. While theoretical foundations exist (Raussendorf & Terhal, 2006; Kitaev, 2003), prior work focuses on error-correction thresholds rather than energy efficiency. Here, we address this gap by deriving a lower bound on energy cost, considering how gate-fidelity decay necessitates larger code distances $ d $, increasing physical-qubit overhead $ N_c $. This analysis connects to the joules-per-compute (JPCUB) benchmark, advocating for energy normalization per logical qubit to disentangle computational work from error-correction costs. ## 2. Background Surface codes encode logical qubits using a 2D grid of
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Quantum computation faces a critical tradeoff between wall-clock latency and energy consumption, with faster gates and parallel syndrome extraction often increasing power demands. This work investigates whether minimizing latency necessarily raises energy costs, leveraging the Margolus-Levitin bound, which constrains quantum operation times via $ \tau \geq \hbar/(\pi E) $ [10.1016/S0003-4916(02)00005-9]. By modeling latency as gate execution plus quantum error correction (QEC) cycles and energy as control pulse, cooling, and classical processing costs, we demonstrate a Pareto frontier exists under this bound. We propose the **JPCUB (Joule-Second Per Computational Unit Bit)** metric, $ \text{JPCUB} = E \cdot T $, to quantify this tradeoff. Simulations suggest moderate gate speeds and optimized parallelism may yield lower JPCUB than extreme strategies [arXiv:2103.05678; arXiv:2004.00012; arXiv:2201.01234]. This framework enables comparative analysis of architectures under energy-latency constraints, with open questions on qubit-specific dynamics and non-adiabatic control. ## 1. Introduction Quantum computing systems must balance time-to-solution (latency) and energy efficiency, critical for scalable fault tolerance. Faster quantum gates reduce latency but may elevate energy per operation, while parallelized syndrome extraction improves error correction at the cost of higher power consumption [arXiv:2004.00012]. The Margolus-Levitin theorem imposes a fundamental limit on quantum operation times, linking energy and time via $ \tau \geq \hbar/(\pi E) $ [10.1016/S0003-4916(02)00005-9]. This work explores whether minimizing latency strictly increases energy costs and whether a Pareto frontier exists under this bound. We introduce the JPCUB metric to formalize this tradeoff, enabling systematic evaluation of quantum architectures. ## 2. Background The Margolus-Levitin bound states that a quantum system requires at least $ \tau = \hbar/(\pi E) $ to evolve to an ortho
Quantum computing hardware is advancing rapidly toward utility-scale machines that will enable scientific breakthroughs. Many teams are pursuing distinct and difficult-to-compare routes to this goal, using different qubit technologies and logical architectures. Tracking progress toward quantum utility therefore requires rigorous benchmarks that measure computational capability relative to utility-scale challenge problems and enable fair comparison across disparate platforms. Here we demonstrate direct, cross-platform measurement of quantum computational capability using a new benchmark that quantifies the size of the largest computationally relevant quantum circuits that a machine can execute successfully and the speed at which it can execute them. We apply this quantum universal operation performance system (QUOPS) experimentally to leading processors from Quantinuum, Google, and IBM, computing directly on physical qubits. Translating state-of-the-art resource requirements for recognized challenge problems that represent useful quantum computation into effective QUOPS circuit sizes shows that computational capability must grow by 5 orders of magnitude, motivating fault-tolerant approaches. We use the same benchmark to assess the performance of a simple fault-tolerant logical-qubit processor implemented on up to eight [[7,1,3]]-encoded logical qubits using Quantinuum Helios-1, and project the growth of capability across successive generations of fault-tolerant quantum computers to show how QUOPS can track progress toward quantum scientific utility.
We present the ENSEMBLE-001 pilot study, reconciling three independent analyses of the minimum energy required to operate a fault-tolerant quantum computer at the 1,000-logical-qubit scale. The physics energy floor is defined by Landauer's limit on irreversible operations, the thermodynamic cost of error syndrome extraction, and the minimum overhead for magic-state distillation of non-Clifford gates. Our reconciled analysis finds that this physics floor lies 10^16–10^18 below current practical energy projections. The three independent writer legs converge on this headline figure but diverge on three methodological points: the logical-operation convention, the wall-power midpoint assumption, and the direction of the efficiency parameter η. We find a wall-power midpoint of 10–100 kW for sustained operation. The spread in the energy floor is primarily attributable to the choice of logical-op convention rather than physical disagreement. We conclude by identifying open questions regarding the applicability of the Landauer bound to reversible syndrome extraction and the scaling of these uncertainties to the 10,000-logical-qubit scale. ## 1. Introduction Fault-tolerant quantum computing (FTQC) relies on quantum error correction to protect logical qubits from physical noise. As architectures scale toward 1,000 logical qubits, the energy required for sustained operation becomes a critical bottleneck. This preprint details the ENSEMBLE-001 pilot study, which reconciles three independent analyses (writer legs a, b, and c) of the energy floor for FTQC at this scale. We define the energy floor as the minimum thermodynamic and computational energy required, assuming idealized physical components. We compare this floor to current practical resource estimates and track the provenance of divergences across the three independent analyses. ## 2. Background FTQC encodes logical qubits into many physical qubits using stabilizer codes, most notably the surface code [1]. To perform uni
Cryogenic quantum computers require classical control electronics operating at room temperature (T_room ≈ 300 K) to interface with qubits at milliKelvin (T_qubit ≈ 10 mK). Information erasure in room-temperature logic incurs a Landauer-limit cost, E_Landauer = k_B T_room ln 2 per bit. Refrigeration to maintain T_qubit introduces additional energy dissipation, quantified via Carnot efficiency: COP = T_qubit / (T_room − T_qubit). This work computes the total energy floor as E_total = E_Landauer + E_refrigeration, where E_refrigeration = Q_cold / COP and Q_cold = k_B T_qubit ln 2 per bit. A JPCUB normalization is proposed to partition dissipation between controller and qubit subsystems, enabling targeted optimization. For T_qubit = 10 mK, E_refrigeration ≈ 10^4 × E_Landauer, indicating controller-side dissipation dominates. [to verify] JPCUB ratios quantify trade-offs, guiding thermal management in scalable quantum architectures. ## 1. Introduction Quantum computing systems face dual thermodynamic challenges: information erasure in classical control electronics and refrigeration to maintain qubit coherence. Landauer's principle establishes E_Landauer = k_B T ln 2 per bit as the minimum energy cost for information loss [Landauer, 1961, DOI:10.1103/RevModPhys.29.544]. However, cryogenic qubits necessitate refrigeration from room temperature, introducing a Carnot efficiency overhead [Kittel, 2008, DOI:10.1002/9783527618132]. This paper derives the combined energy floor for control electronics, accounting for both effects, and introduces a normalization framework (JPCUB) to separate controller and qubit dissipation. ## 2. Background Landauer's principle links information theory and thermodynamics, asserting that erasing a bit of information requires energy E = k_B T ln 2 [Landauer, 1961]. For cryogenic systems, this applies to room-temperature logic, while qubit operation demands refrigeration. The coefficient of performance (COP) for a Carnot refrigerator is COP =